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Commit b3431e57 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: gcc: Add PLL type flag for gpll_out_even clk 



Add PLL type flag for gpll1_out_even and gpll4_out_even
clk to correctly read the user ctl register offset in
recalc rate ops.

Change-Id: I177a31d1ffa88b6ec345c9b604410ba18452a625
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent 788c8028

drivers/clk/qcom/gcc-sdxprairie.c

+3 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -179,6 +179,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { 
	.post_div_table = post_div_table_lucid_even,

	.num_post_div = ARRAY_SIZE(post_div_table_lucid_even),

	.width = 4,

	.type = LUCID_PLL,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll0_out_even",

		.parent_names = (const char *[]){ "gpll0" },
@@ -217,6 +218,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_even = { 
	.post_div_table = post_div_table_lucid_even,

	.num_post_div = ARRAY_SIZE(post_div_table_lucid_even),

	.width = 4,

	.type = LUCID_PLL,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll4_out_even",

		.parent_names = (const char *[]){ "gpll4" },