Loading arch/arm64/boot/dts/qcom/qcs405-coresight.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -71,6 +71,7 @@ arm,buffer-size = <0x400000>; qcom,force-reg-dump; arm,sg-enable; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti0>; Loading arch/arm64/boot/dts/qcom/qcs405.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -405,6 +405,7 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x400>; qcom,curr-link-list = <1>; }; rpm_bus: qcom,rpm-smd { Loading drivers/soc/qcom/dcc_v2.c +2 −2 Original line number Diff line number Diff line Loading @@ -42,7 +42,7 @@ #define dcc_sram_readl(drvdata, off) \ __raw_readl(drvdata->ram_base + off) #define HLOS_LIST_START 1 #define HLOS_LIST_START 0 /* DCC registers */ #define DCC_HW_VERSION (0x00) Loading Loading
arch/arm64/boot/dts/qcom/qcs405-coresight.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -71,6 +71,7 @@ arm,buffer-size = <0x400000>; qcom,force-reg-dump; arm,sg-enable; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti0>; Loading
arch/arm64/boot/dts/qcom/qcs405.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -405,6 +405,7 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x400>; qcom,curr-link-list = <1>; }; rpm_bus: qcom,rpm-smd { Loading
drivers/soc/qcom/dcc_v2.c +2 −2 Original line number Diff line number Diff line Loading @@ -42,7 +42,7 @@ #define dcc_sram_readl(drvdata, off) \ __raw_readl(drvdata->ram_base + off) #define HLOS_LIST_START 1 #define HLOS_LIST_START 0 /* DCC registers */ #define DCC_HW_VERSION (0x00) Loading