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Commit b0f0daa8 authored by Priit Laes's avatar Priit Laes Committed by Maxime Ripard
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clk: sunxi-ng: sun5i: Fix mux width for csi clock 



Mux for CSI clock is 3 bits, not 2.

Signed-off-by: default avatarPriit Laes <plaes@plaes.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 05c04bef

drivers/clk/sunxi-ng/ccu-sun5i.c

+1 −1
Original line number Diff line number Diff line
@@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1", 
static const u8 csi_table[] = { 0, 1, 2, 5, 6 };

static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",

				       csi_parents, csi_table,

				       0x134, 0, 5, 24, 2, BIT(31), 0);

				       0x134, 0, 5, 24, 3, BIT(31), 0);



static SUNXI_CCU_GATE(ve_clk,		"ve",		"pll-ve",

		      0x13c, BIT(31), CLK_SET_RATE_PARENT);