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Commit b0b8a4e8 authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Greg Kroah-Hartman
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drm/bridge: tc358767: add defines for DP1_SRCCTRL & PHY_2LANE 



[ Upstream commit adf4109896bbee27fd2ac3b48d22d6a0062fe517 ]

DP1_SRCCTRL register and PHY_2LANE field did not have matching defines.
Add these.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-3-tomi.valkeinen@ti.com


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 085d2651

drivers/gpu/drm/bridge/tc358767.c

+7 −3
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ 
#define DP0_LTLOOPCTRL		0x06d8

#define DP0_SNKLTCTRL		0x06e4



#define DP1_SRCCTRL		0x07a0



/* PHY */

#define DP_PHY_CTRL		0x0800

#define DP_PHY_RST			BIT(28)  /* DP PHY Global Soft Reset */
@@ -148,6 +150,7 @@ 
#define PHY_M1_RST			BIT(12)  /* Reset PHY1 Main Channel */

#define PHY_RDY				BIT(16)  /* PHY Main Channels Ready */

#define PHY_M0_RST			BIT(8)   /* Reset PHY0 Main Channel */

#define PHY_2LANE			BIT(2)   /* PHY Enable 2 lanes */

#define PHY_A0_EN			BIT(1)   /* PHY Aux Channel0 Enable */

#define PHY_M0_EN			BIT(0)   /* PHY Main Channel0 Enable */
@@ -562,7 +565,7 @@ static int tc_aux_link_setup(struct tc_data *tc) 
	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;

	tc_write(SYS_PLLPARAM, value);



	tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);

	tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN);



	/*

	 * Initially PLLs are in bypass. Force PLL parameter update,
@@ -832,7 +835,7 @@ static int tc_main_link_setup(struct tc_data *tc) 
		 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |

		 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);

	/* from excel file - DP1_SrcCtrl */

	tc_write(0x07a0, 0x00003083);

	tc_write(DP1_SRCCTRL, 0x00003083);



	rate = clk_get_rate(tc->refclk);

	switch (rate) {
@@ -853,8 +856,9 @@ static int tc_main_link_setup(struct tc_data *tc) 
	}

	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;

	tc_write(SYS_PLLPARAM, value);



	/* Setup Main Link */

	dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN |  PHY_M0_EN;

	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN |  PHY_M0_EN;

	tc_write(DP_PHY_CTRL, dp_phy_ctrl);

	msleep(100);