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Commit b08b69a1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 's5p-fixes-for-linus' of... 

Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: S5PV210: Fix regulator names
  ARM: S5PV210: Update max8998_platform_data
  ARM: SAMSUNG: Drop exporting s3c24xx_ts_set_platdata
  ARM: S5P: Fix end address in memory resource information for UART devices
  ARM: S5P64X0: Cleanup map.h file
  ARM: S5P6442: Cleanup map.h file
  ARM: S5PC100: Clenaup map.h file
  ARM: S5PV210: Cleanup map.h file
  ARM: S5PV310: Cleanup map.h file
parents b4f5c462 d1061331

arch/arm/mach-s5p6442/include/mach/map.h

+37 −32
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5p6442/include/mach/map.h

 *

 * Copyright (c) 2010 Samsung Electronics Co., Ltd.

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com/

 *

 * S5P6442 - Memory map definitions
@@ -16,56 +16,61 @@ 
#include <plat/map-base.h>

#include <plat/map-s5p.h>



#define S5P6442_PA_CHIPID	(0xE0000000)

#define S5P_PA_CHIPID		S5P6442_PA_CHIPID

#define S5P6442_PA_SDRAM	0x20000000



#define S5P6442_PA_SYSCON	(0xE0100000)

#define S5P_PA_SYSCON		S5P6442_PA_SYSCON

#define S5P6442_PA_I2S0		0xC0B00000

#define S5P6442_PA_I2S1		0xF2200000



#define S5P6442_PA_GPIO		(0xE0200000)

#define S5P6442_PA_CHIPID	0xE0000000



#define S5P6442_PA_VIC0		(0xE4000000)

#define S5P6442_PA_VIC1		(0xE4100000)

#define S5P6442_PA_VIC2		(0xE4200000)

#define S5P6442_PA_SYSCON	0xE0100000



#define S5P6442_PA_SROMC	(0xE7000000)

#define S5P_PA_SROMC		S5P6442_PA_SROMC

#define S5P6442_PA_GPIO		0xE0200000



#define S5P6442_PA_MDMA		0xE8000000

#define S5P6442_PA_PDMA		0xE9000000

#define S5P6442_PA_VIC0		0xE4000000

#define S5P6442_PA_VIC1		0xE4100000

#define S5P6442_PA_VIC2		0xE4200000



#define S5P6442_PA_TIMER	(0xEA000000)

#define S5P_PA_TIMER		S5P6442_PA_TIMER

#define S5P6442_PA_SROMC	0xE7000000



#define S5P6442_PA_SYSTIMER   	(0xEA100000)

#define S5P6442_PA_MDMA		0xE8000000

#define S5P6442_PA_PDMA		0xE9000000



#define S5P6442_PA_WATCHDOG	(0xEA200000)

#define S5P6442_PA_TIMER	0xEA000000



#define S5P6442_PA_UART		(0xEC000000)

#define S5P6442_PA_SYSTIMER	0xEA100000



#define S5P_PA_UART0		(S5P6442_PA_UART + 0x0)

#define S5P_PA_UART1		(S5P6442_PA_UART + 0x400)

#define S5P_PA_UART2		(S5P6442_PA_UART + 0x800)

#define S5P_SZ_UART		SZ_256

#define S5P6442_PA_WATCHDOG	0xEA200000



#define S5P6442_PA_IIC0		(0xEC100000)

#define S5P6442_PA_UART		0xEC000000



#define S5P6442_PA_SDRAM	(0x20000000)

#define S5P_PA_SDRAM		S5P6442_PA_SDRAM

#define S5P6442_PA_IIC0		0xEC100000



#define S5P6442_PA_SPI		0xEC300000



/* I2S */

#define S5P6442_PA_I2S0		0xC0B00000

#define S5P6442_PA_I2S1		0xF2200000



/* PCM */

#define S5P6442_PA_PCM0		0xF2400000

#define S5P6442_PA_PCM1		0xF2500000



/* compatibiltiy defines. */

/* Compatibiltiy Defines */



#define S3C_PA_IIC		S5P6442_PA_IIC0

#define S3C_PA_WDT		S5P6442_PA_WATCHDOG



#define S5P_PA_CHIPID		S5P6442_PA_CHIPID

#define S5P_PA_SDRAM		S5P6442_PA_SDRAM

#define S5P_PA_SROMC		S5P6442_PA_SROMC

#define S5P_PA_SYSCON		S5P6442_PA_SYSCON

#define S5P_PA_TIMER		S5P6442_PA_TIMER



/* UART */



#define S3C_PA_UART		S5P6442_PA_UART

#define S3C_PA_IIC		S5P6442_PA_IIC0



#define S5P_PA_UART(x)		(S3C_PA_UART + ((x) * S3C_UART_OFFSET))

#define S5P_PA_UART0		S5P_PA_UART(0)

#define S5P_PA_UART1		S5P_PA_UART(1)

#define S5P_PA_UART2		S5P_PA_UART(2)



#define S5P_SZ_UART		SZ_256



#endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s5p64x0/include/mach/map.h

+42 −41
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5p64x0/include/mach/map.h

 *

 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.

 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * S5P64X0 - Memory map definitions
@@ -16,64 +16,46 @@ 
#include <plat/map-base.h>

#include <plat/map-s5p.h>



#define S5P64X0_PA_SDRAM	(0x20000000)

#define S5P64X0_PA_SDRAM	0x20000000



#define S5P64X0_PA_CHIPID	(0xE0000000)

#define S5P_PA_CHIPID		S5P64X0_PA_CHIPID



#define S5P64X0_PA_SYSCON	(0xE0100000)

#define S5P_PA_SYSCON		S5P64X0_PA_SYSCON



#define S5P64X0_PA_GPIO		(0xE0308000)



#define S5P64X0_PA_VIC0		(0xE4000000)

#define S5P64X0_PA_VIC1		(0xE4100000)

#define S5P64X0_PA_CHIPID	0xE0000000



#define S5P64X0_PA_SROMC	(0xE7000000)

#define S5P_PA_SROMC		S5P64X0_PA_SROMC



#define S5P64X0_PA_PDMA		(0xE9000000)



#define S5P64X0_PA_TIMER	(0xEA000000)

#define S5P_PA_TIMER		S5P64X0_PA_TIMER

#define S5P64X0_PA_SYSCON	0xE0100000



#define S5P64X0_PA_RTC		(0xEA100000)

#define S5P64X0_PA_GPIO		0xE0308000



#define S5P64X0_PA_WDT		(0xEA200000)

#define S5P64X0_PA_VIC0		0xE4000000

#define S5P64X0_PA_VIC1		0xE4100000



#define S5P6440_PA_UART(x)	(0xEC000000 + ((x) * S3C_UART_OFFSET))

#define S5P6450_PA_UART(x)	((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))

#define S5P64X0_PA_SROMC	0xE7000000



#define S5P_PA_UART0		S5P6450_PA_UART(0)

#define S5P_PA_UART1		S5P6450_PA_UART(1)

#define S5P_PA_UART2		S5P6450_PA_UART(2)

#define S5P_PA_UART3		S5P6450_PA_UART(3)

#define S5P_PA_UART4		S5P6450_PA_UART(4)

#define S5P_PA_UART5		S5P6450_PA_UART(5)

#define S5P64X0_PA_PDMA		0xE9000000



#define S5P_SZ_UART		SZ_256

#define S5P64X0_PA_TIMER	0xEA000000

#define S5P64X0_PA_RTC		0xEA100000

#define S5P64X0_PA_WDT		0xEA200000



#define S5P6440_PA_IIC0		(0xEC104000)

#define S5P6440_PA_IIC1		(0xEC20F000)

#define S5P6450_PA_IIC0		(0xEC100000)

#define S5P6450_PA_IIC1		(0xEC200000)

#define S5P6440_PA_IIC0		0xEC104000

#define S5P6440_PA_IIC1		0xEC20F000

#define S5P6450_PA_IIC0		0xEC100000

#define S5P6450_PA_IIC1		0xEC200000



#define S5P64X0_PA_SPI0		(0xEC400000)

#define S5P64X0_PA_SPI1		(0xEC500000)

#define S5P64X0_PA_SPI0		0xEC400000

#define S5P64X0_PA_SPI1		0xEC500000



#define S5P64X0_PA_HSOTG	(0xED100000)

#define S5P64X0_PA_HSOTG	0xED100000



#define S5P64X0_PA_HSMMC(x)	(0xED800000 + ((x) * 0x100000))



#define S5P64X0_PA_I2S		(0xF2000000)

#define S5P64X0_PA_I2S		0xF2000000

#define S5P6450_PA_I2S1		0xF2800000

#define S5P6450_PA_I2S2		0xF2900000



#define S5P64X0_PA_PCM		(0xF2100000)

#define S5P64X0_PA_PCM		0xF2100000



#define S5P64X0_PA_ADC		(0xF3000000)

#define S5P64X0_PA_ADC		0xF3000000



/* compatibiltiy defines. */

/* Compatibiltiy Defines */



#define S3C_PA_HSMMC0		S5P64X0_PA_HSMMC(0)

#define S3C_PA_HSMMC1		S5P64X0_PA_HSMMC(1)
@@ -83,6 +65,25 @@ 
#define S3C_PA_RTC		S5P64X0_PA_RTC

#define S3C_PA_WDT		S5P64X0_PA_WDT



#define S5P_PA_CHIPID		S5P64X0_PA_CHIPID

#define S5P_PA_SROMC		S5P64X0_PA_SROMC

#define S5P_PA_SYSCON		S5P64X0_PA_SYSCON

#define S5P_PA_TIMER		S5P64X0_PA_TIMER



#define SAMSUNG_PA_ADC		S5P64X0_PA_ADC



/* UART */



#define S5P6440_PA_UART(x)	(0xEC000000 + ((x) * S3C_UART_OFFSET))

#define S5P6450_PA_UART(x)	((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))



#define S5P_PA_UART0		S5P6450_PA_UART(0)

#define S5P_PA_UART1		S5P6450_PA_UART(1)

#define S5P_PA_UART2		S5P6450_PA_UART(2)

#define S5P_PA_UART3		S5P6450_PA_UART(3)

#define S5P_PA_UART4		S5P6450_PA_UART(4)

#define S5P_PA_UART5		S5P6450_PA_UART(5)



#define S5P_SZ_UART		SZ_256



#endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s5pc100/include/mach/map.h

+83 −110
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5pc100/include/mach/map.h

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com/

 *

 * Copyright 2009 Samsung Electronics Co.

 *	Byungho Min <bhmin@samsung.com>
@@ -16,145 +19,115 @@ 
#include <plat/map-base.h>

#include <plat/map-s5p.h>



/*

 * map-base.h has already defined virtual memory address

 * S3C_VA_IRQ		S3C_ADDR(0x00000000)	irq controller(s)

 * S3C_VA_SYS		S3C_ADDR(0x00100000)	system control

 * S3C_VA_MEM		S3C_ADDR(0x00200000)	system control (not used)

 * S3C_VA_TIMER		S3C_ADDR(0x00300000)	timer block

 * S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	watchdog

 * S3C_VA_UART		S3C_ADDR(0x01000000)	UART

 *

 * S5PC100 specific virtual memory address can be defined here

 * S5PC1XX_VA_GPIO	S3C_ADDR(0x00500000)	GPIO

 *

 */



#define S5PC100_PA_ONENAND_BUF	(0xB0000000)

#define S5PC100_SZ_ONENAND_BUF	(SZ_256M - SZ_32M)



/* Chip ID */



#define S5PC100_PA_CHIPID	(0xE0000000)

#define S5P_PA_CHIPID		S5PC100_PA_CHIPID

#define S5PC100_PA_SDRAM		0x20000000



#define S5PC100_PA_SYSCON	(0xE0100000)

#define S5P_PA_SYSCON		S5PC100_PA_SYSCON

#define S5PC100_PA_ONENAND		0xE7100000

#define S5PC100_PA_ONENAND_BUF		0xB0000000



#define S5PC100_PA_OTHERS	(0xE0200000)

#define S5PC100_VA_OTHERS	(S3C_VA_SYS + 0x10000)

#define S5PC100_PA_CHIPID		0xE0000000



#define S5PC100_PA_GPIO		(0xE0300000)

#define S5PC1XX_VA_GPIO		S3C_ADDR(0x00500000)

#define S5PC100_PA_SYSCON		0xE0100000



/* Interrupt */

#define S5PC100_PA_VIC0		(0xE4000000)

#define S5PC100_PA_VIC1		(0xE4100000)

#define S5PC100_PA_VIC2		(0xE4200000)

#define S5PC100_VA_VIC		S3C_VA_IRQ

#define S5PC100_VA_VIC_OFFSET	0x10000

#define S5PC1XX_VA_VIC(x)	(S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))

#define S5PC100_PA_OTHERS		0xE0200000



#define S5PC100_PA_SROMC	(0xE7000000)

#define S5P_PA_SROMC		S5PC100_PA_SROMC

#define S5PC100_PA_GPIO			0xE0300000



#define S5PC100_PA_ONENAND	(0xE7100000)

#define S5PC100_PA_VIC0			0xE4000000

#define S5PC100_PA_VIC1			0xE4100000

#define S5PC100_PA_VIC2			0xE4200000



#define S5PC100_PA_CFCON	(0xE7800000)

#define S5PC100_PA_SROMC		0xE7000000



/* DMA */

#define S5PC100_PA_MDMA		(0xE8100000)

#define S5PC100_PA_PDMA0	(0xE9000000)

#define S5PC100_PA_PDMA1	(0xE9200000)

#define S5PC100_PA_CFCON		0xE7800000



/* Timer */

#define S5PC100_PA_TIMER	(0xEA000000)

#define S5P_PA_TIMER		S5PC100_PA_TIMER



#define S5PC100_PA_SYSTIMER	(0xEA100000)

#define S5PC100_PA_MDMA			0xE8100000

#define S5PC100_PA_PDMA0		0xE9000000

#define S5PC100_PA_PDMA1		0xE9200000



#define S5PC100_PA_WATCHDOG	(0xEA200000)

#define S5PC100_PA_RTC		(0xEA300000)

#define S5PC100_PA_TIMER		0xEA000000

#define S5PC100_PA_SYSTIMER		0xEA100000

#define S5PC100_PA_WATCHDOG		0xEA200000

#define S5PC100_PA_RTC			0xEA300000



#define S5PC100_PA_UART		(0xEC000000)

#define S5PC100_PA_UART			0xEC000000



#define S5P_PA_UART0		(S5PC100_PA_UART + 0x0)

#define S5P_PA_UART1		(S5PC100_PA_UART + 0x400)

#define S5P_PA_UART2		(S5PC100_PA_UART + 0x800)

#define S5P_PA_UART3		(S5PC100_PA_UART + 0xC00)

#define S5P_SZ_UART		SZ_256

#define S5PC100_PA_IIC0			0xEC100000

#define S5PC100_PA_IIC1			0xEC200000



#define S5PC100_PA_IIC0		(0xEC100000)

#define S5PC100_PA_IIC1		(0xEC200000)



/* SPI */

#define S5PC100_PA_SPI0			0xEC300000

#define S5PC100_PA_SPI1			0xEC400000

#define S5PC100_PA_SPI2			0xEC500000



/* USB HS OTG */

#define S5PC100_PA_USB_HSOTG	(0xED200000)

#define S5PC100_PA_USB_HSPHY	(0xED300000)

#define S5PC100_PA_USB_HSOTG		0xED200000

#define S5PC100_PA_USB_HSPHY		0xED300000



#define S5PC100_PA_HSMMC(x)		(0xED800000 + ((x) * 0x100000))



#define S5PC100_PA_FB		(0xEE000000)

#define S5PC100_PA_FB			0xEE000000



#define S5PC100_PA_FIMC0	(0xEE200000)

#define S5PC100_PA_FIMC1	(0xEE300000)

#define S5PC100_PA_FIMC2	(0xEE400000)

#define S5PC100_PA_FIMC0		0xEE200000

#define S5PC100_PA_FIMC1		0xEE300000

#define S5PC100_PA_FIMC2		0xEE400000



#define S5PC100_PA_I2S0		(0xF2000000)

#define S5PC100_PA_I2S1		(0xF2100000)

#define S5PC100_PA_I2S2		(0xF2200000)

#define S5PC100_PA_I2S0			0xF2000000

#define S5PC100_PA_I2S1			0xF2100000

#define S5PC100_PA_I2S2			0xF2200000



#define S5PC100_PA_AC97			0xF2300000



/* PCM */

#define S5PC100_PA_PCM0			0xF2400000

#define S5PC100_PA_PCM1			0xF2500000



#define S5PC100_PA_SPDIF		0xF2600000



#define S5PC100_PA_TSADC	(0xF3000000)

#define S5PC100_PA_TSADC		0xF3000000



/* KEYPAD */

#define S5PC100_PA_KEYPAD	(0xF3100000)

#define S5PC100_PA_KEYPAD		0xF3100000



#define S5PC100_PA_HSMMC(x)	(0xED800000 + ((x) * 0x100000))

/* Compatibiltiy Defines */



#define S5PC100_PA_SDRAM	(0x20000000)

#define S5P_PA_SDRAM		S5PC100_PA_SDRAM



/* compatibiltiy defines. */

#define S3C_PA_UART		S5PC100_PA_UART

#define S3C_PA_IIC		S5PC100_PA_IIC0

#define S3C_PA_IIC1		S5PC100_PA_IIC1

#define S3C_PA_FB			S5PC100_PA_FB

#define S3C_PA_G2D		S5PC100_PA_G2D

#define S3C_PA_G3D		S5PC100_PA_G3D

#define S3C_PA_JPEG		S5PC100_PA_JPEG

#define S3C_PA_ROTATOR		S5PC100_PA_ROTATOR

#define S5P_VA_VIC0		S5PC1XX_VA_VIC(0)

#define S5P_VA_VIC1		S5PC1XX_VA_VIC(1)

#define S5P_VA_VIC2		S5PC1XX_VA_VIC(2)

#define S3C_PA_USB_HSOTG	S5PC100_PA_USB_HSOTG

#define S3C_PA_USB_HSPHY	S5PC100_PA_USB_HSPHY

#define S3C_PA_HSMMC0			S5PC100_PA_HSMMC(0)

#define S3C_PA_HSMMC1			S5PC100_PA_HSMMC(1)

#define S3C_PA_HSMMC2			S5PC100_PA_HSMMC(2)

#define S3C_PA_IIC			S5PC100_PA_IIC0

#define S3C_PA_IIC1			S5PC100_PA_IIC1

#define S3C_PA_KEYPAD			S5PC100_PA_KEYPAD

#define S3C_PA_WDT		S5PC100_PA_WATCHDOG

#define S3C_PA_TSADC		S5PC100_PA_TSADC

#define S3C_PA_ONENAND			S5PC100_PA_ONENAND

#define S3C_PA_ONENAND_BUF		S5PC100_PA_ONENAND_BUF

#define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF

#define S3C_PA_RTC			S5PC100_PA_RTC

#define S3C_PA_TSADC			S5PC100_PA_TSADC

#define S3C_PA_USB_HSOTG		S5PC100_PA_USB_HSOTG

#define S3C_PA_USB_HSPHY		S5PC100_PA_USB_HSPHY

#define S3C_PA_WDT			S5PC100_PA_WATCHDOG



#define S5P_PA_CHIPID			S5PC100_PA_CHIPID

#define S5P_PA_FIMC0			S5PC100_PA_FIMC0

#define S5P_PA_FIMC1			S5PC100_PA_FIMC1

#define S5P_PA_FIMC2			S5PC100_PA_FIMC2

#define S5P_PA_SDRAM			S5PC100_PA_SDRAM

#define S5P_PA_SROMC			S5PC100_PA_SROMC

#define S5P_PA_SYSCON			S5PC100_PA_SYSCON

#define S5P_PA_TIMER			S5PC100_PA_TIMER



#define SAMSUNG_PA_ADC			S5PC100_PA_TSADC

#define SAMSUNG_PA_CFCON		S5PC100_PA_CFCON

#define SAMSUNG_PA_KEYPAD		S5PC100_PA_KEYPAD



#define S5P_PA_FIMC0		S5PC100_PA_FIMC0

#define S5P_PA_FIMC1		S5PC100_PA_FIMC1

#define S5P_PA_FIMC2		S5PC100_PA_FIMC2

#define S5PC100_VA_OTHERS		(S3C_VA_SYS + 0x10000)



#define S3C_SZ_ONENAND_BUF		(SZ_256M - SZ_32M)



/* UART */



#define S3C_PA_UART			S5PC100_PA_UART



#define S5P_PA_UART(x)			(S3C_PA_UART + ((x) * S3C_UART_OFFSET))

#define S5P_PA_UART0			S5P_PA_UART(0)

#define S5P_PA_UART1			S5P_PA_UART(1)

#define S5P_PA_UART2			S5P_PA_UART(2)

#define S5P_PA_UART3			S5P_PA_UART(3)



#define S5P_SZ_UART			SZ_256



#endif /* __ASM_ARCH_C100_MAP_H */
 
#endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s5pv210/include/mach/map.h

+83 −85
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-s5pv210/include/mach/map.h

 *

 * Copyright (c) 2010 Samsung Electronics Co., Ltd.

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com/

 *

 * S5PV210 - Memory map definitions
@@ -16,104 +16,81 @@ 
#include <plat/map-base.h>

#include <plat/map-s5p.h>



#define S5PV210_PA_SROM_BANK5	(0xA8000000)

#define S5PV210_PA_SDRAM		0x20000000



#define S5PC110_PA_ONENAND	(0xB0000000)

#define S5P_PA_ONENAND		S5PC110_PA_ONENAND

#define S5PV210_PA_SROM_BANK5		0xA8000000



#define S5PC110_PA_ONENAND_DMA	(0xB0600000)

#define S5P_PA_ONENAND_DMA	S5PC110_PA_ONENAND_DMA

#define S5PC110_PA_ONENAND		0xB0000000

#define S5PC110_PA_ONENAND_DMA		0xB0600000



#define S5PV210_PA_CHIPID	(0xE0000000)

#define S5P_PA_CHIPID		S5PV210_PA_CHIPID

#define S5PV210_PA_CHIPID		0xE0000000



#define S5PV210_PA_SYSCON	(0xE0100000)

#define S5P_PA_SYSCON		S5PV210_PA_SYSCON

#define S5PV210_PA_SYSCON		0xE0100000



#define S5PV210_PA_GPIO		(0xE0200000)

#define S5PV210_PA_GPIO			0xE0200000



#define S5PV210_PA_SPDIF		0xE1100000



/* SPI */

#define S5PV210_PA_SPI0			0xE1300000

#define S5PV210_PA_SPI1			0xE1400000



#define S5PV210_PA_KEYPAD	(0xE1600000)

#define S5PV210_PA_KEYPAD		0xE1600000



#define S5PV210_PA_IIC0		(0xE1800000)

#define S5PV210_PA_IIC1		(0xFAB00000)

#define S5PV210_PA_IIC2		(0xE1A00000)



#define S5PV210_PA_TIMER	(0xE2500000)

#define S5P_PA_TIMER		S5PV210_PA_TIMER

#define S5PV210_PA_ADC			0xE1700000



#define S5PV210_PA_SYSTIMER	(0xE2600000)

#define S5PV210_PA_IIC0			0xE1800000

#define S5PV210_PA_IIC1			0xFAB00000

#define S5PV210_PA_IIC2			0xE1A00000



#define S5PV210_PA_WATCHDOG	(0xE2700000)



#define S5PV210_PA_RTC		(0xE2800000)

#define S5PV210_PA_UART		(0xE2900000)



#define S5P_PA_UART0		(S5PV210_PA_UART + 0x0)

#define S5P_PA_UART1		(S5PV210_PA_UART + 0x400)

#define S5P_PA_UART2		(S5PV210_PA_UART + 0x800)

#define S5P_PA_UART3		(S5PV210_PA_UART + 0xC00)



#define S5P_SZ_UART		SZ_256



#define S3C_VA_UARTx(x)		(S3C_VA_UART + ((x) * S3C_UART_OFFSET))

#define S5PV210_PA_AC97			0xE2200000



#define S5PV210_PA_SROMC	(0xE8000000)

#define S5P_PA_SROMC		S5PV210_PA_SROMC

#define S5PV210_PA_PCM0			0xE2300000

#define S5PV210_PA_PCM1			0xE1200000

#define S5PV210_PA_PCM2			0xE2B00000



#define S5PV210_PA_CFCON	(0xE8200000)

#define S5PV210_PA_TIMER		0xE2500000

#define S5PV210_PA_SYSTIMER		0xE2600000

#define S5PV210_PA_WATCHDOG		0xE2700000

#define S5PV210_PA_RTC			0xE2800000



#define S5PV210_PA_MDMA		0xFA200000

#define S5PV210_PA_PDMA0	0xE0900000

#define S5PV210_PA_PDMA1	0xE0A00000

#define S5PV210_PA_UART			0xE2900000



#define S5PV210_PA_FB		(0xF8000000)

#define S5PV210_PA_SROMC		0xE8000000



#define S5PV210_PA_FIMC0	(0xFB200000)

#define S5PV210_PA_FIMC1	(0xFB300000)

#define S5PV210_PA_FIMC2	(0xFB400000)

#define S5PV210_PA_CFCON		0xE8200000



#define S5PV210_PA_HSMMC(x)		(0xEB000000 + ((x) * 0x100000))



#define S5PV210_PA_HSOTG	(0xEC000000)

#define S5PV210_PA_HSPHY	(0xEC100000)

#define S5PV210_PA_HSOTG		0xEC000000

#define S5PV210_PA_HSPHY		0xEC100000



#define S5PV210_PA_VIC0		(0xF2000000)

#define S5PV210_PA_VIC1		(0xF2100000)

#define S5PV210_PA_VIC2		(0xF2200000)

#define S5PV210_PA_VIC3		(0xF2300000)



#define S5PV210_PA_SDRAM	(0x20000000)

#define S5P_PA_SDRAM		S5PV210_PA_SDRAM



/* S/PDIF */

#define S5PV210_PA_SPDIF	0xE1100000



/* I2S */

#define S5PV210_PA_IIS0			0xEEE30000

#define S5PV210_PA_IIS1			0xE2100000

#define S5PV210_PA_IIS2			0xE2A00000



/* PCM */

#define S5PV210_PA_PCM0		0xE2300000

#define S5PV210_PA_PCM1		0xE1200000

#define S5PV210_PA_PCM2		0xE2B00000

#define S5PV210_PA_DMC0			0xF0000000

#define S5PV210_PA_DMC1			0xF1400000



/* AC97 */

#define S5PV210_PA_AC97		0xE2200000

#define S5PV210_PA_VIC0			0xF2000000

#define S5PV210_PA_VIC1			0xF2100000

#define S5PV210_PA_VIC2			0xF2200000

#define S5PV210_PA_VIC3			0xF2300000



#define S5PV210_PA_ADC		(0xE1700000)

#define S5PV210_PA_FB			0xF8000000



#define S5PV210_PA_DMC0		(0xF0000000)

#define S5PV210_PA_DMC1		(0xF1400000)

#define S5PV210_PA_MDMA			0xFA200000

#define S5PV210_PA_PDMA0		0xE0900000

#define S5PV210_PA_PDMA1		0xE0A00000



#define S5PV210_PA_MIPI_CSIS		0xFA600000



/* compatibiltiy defines. */

#define S3C_PA_UART		S5PV210_PA_UART

#define S5PV210_PA_FIMC0		0xFB200000

#define S5PV210_PA_FIMC1		0xFB300000

#define S5PV210_PA_FIMC2		0xFB400000



/* Compatibiltiy Defines */



#define S3C_PA_FB			S5PV210_PA_FB

#define S3C_PA_HSMMC0			S5PV210_PA_HSMMC(0)

#define S3C_PA_HSMMC1			S5PV210_PA_HSMMC(1)

#define S3C_PA_HSMMC2			S5PV210_PA_HSMMC(2)
@@ -121,17 +98,38 @@ 
#define S3C_PA_IIC			S5PV210_PA_IIC0

#define S3C_PA_IIC1			S5PV210_PA_IIC1

#define S3C_PA_IIC2			S5PV210_PA_IIC2

#define S3C_PA_FB		S5PV210_PA_FB

#define S3C_PA_RTC			S5PV210_PA_RTC

#define S3C_PA_WDT		S5PV210_PA_WATCHDOG

#define S3C_PA_USB_HSOTG		S5PV210_PA_HSOTG

#define S3C_PA_WDT			S5PV210_PA_WATCHDOG



#define S5P_PA_CHIPID			S5PV210_PA_CHIPID

#define S5P_PA_FIMC0			S5PV210_PA_FIMC0

#define S5P_PA_FIMC1			S5PV210_PA_FIMC1

#define S5P_PA_FIMC2			S5PV210_PA_FIMC2

#define S5P_PA_MIPI_CSIS0		S5PV210_PA_MIPI_CSIS

#define S5P_PA_ONENAND			S5PC110_PA_ONENAND

#define S5P_PA_ONENAND_DMA		S5PC110_PA_ONENAND_DMA

#define S5P_PA_SDRAM			S5PV210_PA_SDRAM

#define S5P_PA_SROMC			S5PV210_PA_SROMC

#define S5P_PA_SYSCON			S5PV210_PA_SYSCON

#define S5P_PA_TIMER			S5PV210_PA_TIMER



#define SAMSUNG_PA_ADC			S5PV210_PA_ADC

#define SAMSUNG_PA_CFCON		S5PV210_PA_CFCON

#define SAMSUNG_PA_KEYPAD		S5PV210_PA_KEYPAD



/* UART */



#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))



#define S3C_PA_UART			S5PV210_PA_UART



#define S5P_PA_UART(x)			(S3C_PA_UART + ((x) * S3C_UART_OFFSET))

#define S5P_PA_UART0			S5P_PA_UART(0)

#define S5P_PA_UART1			S5P_PA_UART(1)

#define S5P_PA_UART2			S5P_PA_UART(2)

#define S5P_PA_UART3			S5P_PA_UART(3)



#define S5P_SZ_UART			SZ_256



#endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s5pv210/mach-aquila.c

+9 −6
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = { 


static struct regulator_init_data aquila_ldo3_data = {

	.constraints	= {

		.name		= "VUSB/MIPI_1.1V",

		.name		= "VUSB+MIPI_1.1V",

		.min_uV		= 1100000,

		.max_uV		= 1100000,

		.apply_uV	= 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = { 


static struct regulator_init_data aquila_ldo8_data = {

	.constraints	= {

		.name		= "VUSB/VADC_3.3V",

		.name		= "VUSB+VADC_3.3V",

		.min_uV		= 3300000,

		.max_uV		= 3300000,

		.apply_uV	= 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = { 


static struct regulator_init_data aquila_ldo9_data = {

	.constraints	= {

		.name		= "VCC/VCAM_2.8V",

		.name		= "VCC+VCAM_2.8V",

		.min_uV		= 2800000,

		.max_uV		= 2800000,

		.apply_uV	= 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = { 
	.buck1_set1	= S5PV210_GPH0(3),

	.buck1_set2	= S5PV210_GPH0(4),

	.buck2_set3	= S5PV210_GPH0(5),

	.buck1_max_voltage1 = 1200000,

	.buck1_max_voltage2 = 1200000,

	.buck2_max_voltage = 1200000,

	.buck1_voltage1	= 1200000,

	.buck1_voltage2	= 1200000,

	.buck1_voltage3	= 1200000,

	.buck1_voltage4	= 1200000,

	.buck2_voltage1	= 1200000,

	.buck2_voltage2	= 1200000,

};

#endif