Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b0272276 authored by Pingchao Yang's avatar Pingchao Yang Committed by Herbert Xu
Browse files

crypto: qat - add support for new devices to FW loader 



FW loader updates for new qat devices

Signed-off-by: default avatarTadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 9809ebcd

drivers/crypto/qat/qat_common/adf_accel_engine.c

+6 −3
Original line number Original line Diff line number Diff line
@@ -78,9 +78,12 @@ int adf_ae_fw_load(struct adf_accel_dev *accel_dev) 
	uof_addr = (void *)loader_data->uof_fw->data;

	uof_addr = (void *)loader_data->uof_fw->data;

	mmp_size = loader_data->mmp_fw->size;

	mmp_size = loader_data->mmp_fw->size;

	mmp_addr = (void *)loader_data->mmp_fw->data;

	mmp_addr = (void *)loader_data->mmp_fw->data;

	qat_uclo_wr_mimage(loader_data->fw_loader, mmp_addr, mmp_size);

	if (qat_uclo_wr_mimage(loader_data->fw_loader, mmp_addr, mmp_size)) {

	if (qat_uclo_map_uof_obj(loader_data->fw_loader, uof_addr, uof_size)) {

		dev_err(&GET_DEV(accel_dev), "Failed to load MMP\n");

		dev_err(&GET_DEV(accel_dev), "Failed to map UOF\n");

		goto out_err;

	}

	if (qat_uclo_map_obj(loader_data->fw_loader, uof_addr, uof_size)) {

		dev_err(&GET_DEV(accel_dev), "Failed to map FW\n");

		goto out_err;

		goto out_err;

	}

	}

	if (qat_uclo_wr_all_uimage(loader_data->fw_loader)) {

	if (qat_uclo_wr_all_uimage(loader_data->fw_loader)) {

drivers/crypto/qat/qat_common/adf_common_drv.h

+6 −4
Original line number Original line Diff line number Diff line
@@ -178,6 +178,8 @@ void qat_hal_reset(struct icp_qat_fw_loader_handle *handle); 
int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle);

int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle);

void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle,

void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle,

			  unsigned char ae, unsigned int ctx_mask);

			  unsigned char ae, unsigned int ctx_mask);

int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,

			    unsigned int ae);

int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle,

int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle,

			   unsigned char ae, enum icp_qat_uof_regtype lm_type,

			   unsigned char ae, enum icp_qat_uof_regtype lm_type,

			   unsigned char mode);

			   unsigned char mode);
@@ -216,9 +218,9 @@ int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle, 
		  unsigned char ae, unsigned short lm_addr, unsigned int value);

		  unsigned char ae, unsigned short lm_addr, unsigned int value);

int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);

int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);

void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle);

void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle);

int qat_uclo_map_uof_obj(struct icp_qat_fw_loader_handle *handle,

int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,

			 void *addr_ptr, int mem_size);

		       int mem_size);

void qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle,

int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,

		     void *addr_ptr, int mem_size);

		     void *addr_ptr, int mem_size);

#if defined(CONFIG_PCI_IOV)

#if defined(CONFIG_PCI_IOV)

int adf_sriov_configure(struct pci_dev *pdev, int numvfs);

int adf_sriov_configure(struct pci_dev *pdev, int numvfs);

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h

+10 −0
Original line number Original line Diff line number Diff line
@@ -68,11 +68,21 @@ struct icp_qat_fw_loader_hal_handle { 




struct icp_qat_fw_loader_handle {

struct icp_qat_fw_loader_handle {

	struct icp_qat_fw_loader_hal_handle *hal_handle;

	struct icp_qat_fw_loader_hal_handle *hal_handle;

	struct pci_dev *pci_dev;

	void *obj_handle;

	void *obj_handle;

	void *sobj_handle;

	bool fw_auth;

	void __iomem *hal_sram_addr_v;

	void __iomem *hal_sram_addr_v;

	void __iomem *hal_cap_g_ctl_csr_addr_v;

	void __iomem *hal_cap_g_ctl_csr_addr_v;

	void __iomem *hal_cap_ae_xfer_csr_addr_v;

	void __iomem *hal_cap_ae_xfer_csr_addr_v;

	void __iomem *hal_cap_ae_local_csr_addr_v;

	void __iomem *hal_cap_ae_local_csr_addr_v;

	void __iomem *hal_ep_csr_addr_v;

	void __iomem *hal_ep_csr_addr_v;

};

};



struct icp_firml_dram_desc {

	void __iomem *dram_base_addr;

	void *dram_base_addr_v;

	dma_addr_t dram_bus_addr;

	u64 dram_size;

};

#endif
 
#endif

drivers/crypto/qat/qat_common/icp_qat_hal.h

+34 −3
Original line number Original line Diff line number Diff line
@@ -81,6 +81,31 @@ enum hal_ae_csr { 
	LOCAL_CSR_STATUS = 0x180,

	LOCAL_CSR_STATUS = 0x180,

};

};





enum fcu_csr {

	FCU_CONTROL           = 0x8c0,

	FCU_STATUS            = 0x8c4,

	FCU_STATUS1           = 0x8c8,

	FCU_DRAM_ADDR_LO      = 0x8cc,

	FCU_DRAM_ADDR_HI      = 0x8d0,

	FCU_RAMBASE_ADDR_HI   = 0x8d4,

	FCU_RAMBASE_ADDR_LO   = 0x8d8

};



enum fcu_cmd {

	FCU_CTRL_CMD_NOOP  = 0,

	FCU_CTRL_CMD_AUTH  = 1,

	FCU_CTRL_CMD_LOAD  = 2,

	FCU_CTRL_CMD_START = 3

};



enum fcu_sts {

	FCU_STS_NO_STS    = 0,

	FCU_STS_VERI_DONE = 1,

	FCU_STS_LOAD_DONE = 2,

	FCU_STS_VERI_FAIL = 3,

	FCU_STS_LOAD_FAIL = 4,

	FCU_STS_BUSY      = 5

};

#define UA_ECS                      (0x1 << 31)

#define UA_ECS                      (0x1 << 31)

#define ACS_ABO_BITPOS              31

#define ACS_ABO_BITPOS              31

#define ACS_ACNO                    0x7

#define ACS_ACNO                    0x7
@@ -98,6 +123,13 @@ enum hal_ae_csr { 
#define LCS_STATUS          (0x1)

#define LCS_STATUS          (0x1)

#define MMC_SHARE_CS_BITPOS         2

#define MMC_SHARE_CS_BITPOS         2

#define GLOBAL_CSR                0xA00

#define GLOBAL_CSR                0xA00

#define FCU_CTRL_AE_POS     0x8

#define FCU_AUTH_STS_MASK   0x7

#define FCU_STS_DONE_POS    0x9

#define FCU_STS_AUTHFWLD_POS 0X8

#define FCU_LOADED_AE_POS   0x16

#define FW_AUTH_WAIT_PERIOD 10

#define FW_AUTH_MAX_RETRY   300





#define SET_CAP_CSR(handle, csr, val) \

#define SET_CAP_CSR(handle, csr, val) \

	ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)

	ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
@@ -106,14 +138,14 @@ enum hal_ae_csr { 
#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)

#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)

#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)

#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)

#define AE_CSR(handle, ae) \

#define AE_CSR(handle, ae) \

	(handle->hal_cap_ae_local_csr_addr_v + \

	((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \

	((ae & handle->hal_handle->ae_mask) << 12))

	((ae & handle->hal_handle->ae_mask) << 12))

#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))

#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))

#define SET_AE_CSR(handle, ae, csr, val) \

#define SET_AE_CSR(handle, ae, csr, val) \

	ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)

	ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)

#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)

#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)

#define AE_XFER(handle, ae) \

#define AE_XFER(handle, ae) \

	(handle->hal_cap_ae_xfer_csr_addr_v + \

	((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \

	((ae & handle->hal_handle->ae_mask) << 12))

	((ae & handle->hal_handle->ae_mask) << 12))

#define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \

#define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \

	((reg & 0xff) << 2))

	((reg & 0xff) << 2))
@@ -121,5 +153,4 @@ enum hal_ae_csr { 
	ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)

	ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)

#define SRAM_WRITE(handle, addr, val) \

#define SRAM_WRITE(handle, addr, val) \

	ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)

	ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)

#define SRAM_READ(handle, addr) ADF_CSR_RD(handle->hal_sram_addr_v, addr)

#endif
 
#endif

drivers/crypto/qat/qat_common/icp_qat_uclo.h

+158 −7
Original line number Original line Diff line number Diff line
@@ -47,32 +47,55 @@ 
#ifndef __ICP_QAT_UCLO_H__

#ifndef __ICP_QAT_UCLO_H__

#define __ICP_QAT_UCLO_H__

#define __ICP_QAT_UCLO_H__





#define ICP_QAT_AC_C_CPU_TYPE     0x00400000

#define ICP_QAT_AC_895XCC_DEV_TYPE 0x00400000

#define ICP_QAT_AC_C62X_DEV_TYPE   0x01000000

#define ICP_QAT_AC_C3XXX_DEV_TYPE  0x02000000

#define ICP_QAT_UCLO_MAX_AE       12

#define ICP_QAT_UCLO_MAX_AE       12

#define ICP_QAT_UCLO_MAX_CTX      8

#define ICP_QAT_UCLO_MAX_CTX      8

#define ICP_QAT_UCLO_MAX_UIMAGE   (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)

#define ICP_QAT_UCLO_MAX_UIMAGE   (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)

#define ICP_QAT_UCLO_MAX_USTORE   0x4000

#define ICP_QAT_UCLO_MAX_USTORE   0x4000

#define ICP_QAT_UCLO_MAX_XFER_REG 128

#define ICP_QAT_UCLO_MAX_XFER_REG 128

#define ICP_QAT_UCLO_MAX_GPR_REG  128

#define ICP_QAT_UCLO_MAX_GPR_REG  128

#define ICP_QAT_UCLO_MAX_NN_REG   128

#define ICP_QAT_UCLO_MAX_LMEM_REG 1024

#define ICP_QAT_UCLO_MAX_LMEM_REG 1024

#define ICP_QAT_UCLO_AE_ALL_CTX   0xff

#define ICP_QAT_UCLO_AE_ALL_CTX   0xff

#define ICP_QAT_UOF_OBJID_LEN     8

#define ICP_QAT_UOF_OBJID_LEN     8

#define ICP_QAT_UOF_FID 0xc6c2

#define ICP_QAT_UOF_FID 0xc6c2

#define ICP_QAT_UOF_MAJVER 0x4

#define ICP_QAT_UOF_MAJVER 0x4

#define ICP_QAT_UOF_MINVER 0x11

#define ICP_QAT_UOF_MINVER 0x11

#define ICP_QAT_UOF_NN_MODE_NOTCARE   0xff

#define ICP_QAT_UOF_OBJS        "UOF_OBJS"

#define ICP_QAT_UOF_OBJS        "UOF_OBJS"

#define ICP_QAT_UOF_STRT        "UOF_STRT"

#define ICP_QAT_UOF_STRT        "UOF_STRT"

#define ICP_QAT_UOF_GTID        "UOF_GTID"

#define ICP_QAT_UOF_IMAG        "UOF_IMAG"

#define ICP_QAT_UOF_IMAG        "UOF_IMAG"

#define ICP_QAT_UOF_IMEM        "UOF_IMEM"

#define ICP_QAT_UOF_IMEM        "UOF_IMEM"

#define ICP_QAT_UOF_MSEG        "UOF_MSEG"

#define ICP_QAT_UOF_LOCAL_SCOPE     1

#define ICP_QAT_UOF_LOCAL_SCOPE     1

#define ICP_QAT_UOF_INIT_EXPR               0

#define ICP_QAT_UOF_INIT_EXPR               0

#define ICP_QAT_UOF_INIT_REG                1

#define ICP_QAT_UOF_INIT_REG                1

#define ICP_QAT_UOF_INIT_REG_CTX            2

#define ICP_QAT_UOF_INIT_REG_CTX            2

#define ICP_QAT_UOF_INIT_EXPR_ENDIAN_SWAP   3

#define ICP_QAT_UOF_INIT_EXPR_ENDIAN_SWAP   3

#define ICP_QAT_SUOF_OBJ_ID_LEN             8

#define ICP_QAT_SUOF_FID  0x53554f46

#define ICP_QAT_SUOF_MAJVER 0x0

#define ICP_QAT_SUOF_MINVER 0x1

#define ICP_QAT_SIMG_AE_INIT_SEQ_LEN    (50 * sizeof(unsigned long long))

#define ICP_QAT_SIMG_AE_INSTS_LEN       (0x4000 * sizeof(unsigned long long))

#define ICP_QAT_CSS_FWSK_MODULUS_LEN    256

#define ICP_QAT_CSS_FWSK_EXPONENT_LEN   4

#define ICP_QAT_CSS_FWSK_PAD_LEN        252

#define ICP_QAT_CSS_FWSK_PUB_LEN   (ICP_QAT_CSS_FWSK_MODULUS_LEN + \

				    ICP_QAT_CSS_FWSK_EXPONENT_LEN + \

				    ICP_QAT_CSS_FWSK_PAD_LEN)

#define ICP_QAT_CSS_SIGNATURE_LEN   256

#define ICP_QAT_CSS_AE_IMG_LEN     (sizeof(struct icp_qat_simg_ae_mode) + \

				    ICP_QAT_SIMG_AE_INIT_SEQ_LEN +         \

				    ICP_QAT_SIMG_AE_INSTS_LEN)

#define ICP_QAT_CSS_AE_SIMG_LEN    (sizeof(struct icp_qat_css_hdr) + \

				    ICP_QAT_CSS_FWSK_PUB_LEN + \

				    ICP_QAT_CSS_SIGNATURE_LEN + \

				    ICP_QAT_CSS_AE_IMG_LEN)

#define ICP_QAT_AE_IMG_OFFSET	   (sizeof(struct icp_qat_css_hdr) + \

				    ICP_QAT_CSS_FWSK_MODULUS_LEN + \

				    ICP_QAT_CSS_FWSK_EXPONENT_LEN + \

				    ICP_QAT_CSS_SIGNATURE_LEN)

#define ICP_QAT_CSS_MAX_IMAGE_LEN   0x40000





#define ICP_QAT_CTX_MODE(ae_mode) ((ae_mode) & 0xf)

#define ICP_QAT_CTX_MODE(ae_mode) ((ae_mode) & 0xf)

#define ICP_QAT_NN_MODE(ae_mode) (((ae_mode) >> 0x4) & 0xf)

#define ICP_QAT_NN_MODE(ae_mode) (((ae_mode) >> 0x4) & 0xf)
@@ -112,6 +135,11 @@ enum icp_qat_uof_regtype { 
	ICP_NEIGH_REL,

	ICP_NEIGH_REL,

};

};





enum icp_qat_css_fwtype {

	CSS_AE_FIRMWARE = 0,

	CSS_MMP_FIRMWARE = 1

};



struct icp_qat_uclo_page {

struct icp_qat_uclo_page {

	struct icp_qat_uclo_encap_page *encap_page;

	struct icp_qat_uclo_encap_page *encap_page;

	struct icp_qat_uclo_region *region;

	struct icp_qat_uclo_region *region;
@@ -235,7 +263,7 @@ struct icp_qat_uof_filechunkhdr { 
};

};





struct icp_qat_uof_objhdr {

struct icp_qat_uof_objhdr {

	unsigned int cpu_type;

	unsigned int ac_dev_type;

	unsigned short min_cpu_ver;

	unsigned short min_cpu_ver;

	unsigned short max_cpu_ver;

	unsigned short max_cpu_ver;

	short max_chunks;

	short max_chunks;
@@ -326,7 +354,7 @@ struct icp_qat_uof_image { 
	unsigned int img_name;

	unsigned int img_name;

	unsigned int ae_assigned;

	unsigned int ae_assigned;

	unsigned int ctx_assigned;

	unsigned int ctx_assigned;

	unsigned int cpu_type;

	unsigned int ac_dev_type;

	unsigned int entry_address;

	unsigned int entry_address;

	unsigned int fill_pattern[2];

	unsigned int fill_pattern[2];

	unsigned int reloadable_size;

	unsigned int reloadable_size;
@@ -374,4 +402,127 @@ struct icp_qat_uof_batch_init { 
	unsigned int size;

	unsigned int size;

	struct icp_qat_uof_batch_init *next;

	struct icp_qat_uof_batch_init *next;

};

};



struct icp_qat_suof_img_hdr {

	char          *simg_buf;

	unsigned long simg_len;

	char          *css_header;

	char          *css_key;

	char          *css_signature;

	char          *css_simg;

	unsigned long simg_size;

	unsigned int  ae_num;

	unsigned int  ae_mask;

	unsigned int  fw_type;

	unsigned long simg_name;

	unsigned long appmeta_data;

};



struct icp_qat_suof_img_tbl {

	unsigned int num_simgs;

	struct icp_qat_suof_img_hdr *simg_hdr;

};



struct icp_qat_suof_handle {

	unsigned int  file_id;

	unsigned int  check_sum;

	char          min_ver;

	char          maj_ver;

	char          fw_type;

	char          *suof_buf;

	unsigned int  suof_size;

	char          *sym_str;

	unsigned int  sym_size;

	struct icp_qat_suof_img_tbl img_table;

};



struct icp_qat_fw_auth_desc {

	unsigned int   img_len;

	unsigned int   reserved;

	unsigned int   css_hdr_high;

	unsigned int   css_hdr_low;

	unsigned int   img_high;

	unsigned int   img_low;

	unsigned int   signature_high;

	unsigned int   signature_low;

	unsigned int   fwsk_pub_high;

	unsigned int   fwsk_pub_low;

	unsigned int   img_ae_mode_data_high;

	unsigned int   img_ae_mode_data_low;

	unsigned int   img_ae_init_data_high;

	unsigned int   img_ae_init_data_low;

	unsigned int   img_ae_insts_high;

	unsigned int   img_ae_insts_low;

};



struct icp_qat_auth_chunk {

	struct icp_qat_fw_auth_desc fw_auth_desc;

	u64 chunk_size;

	u64 chunk_bus_addr;

};



struct icp_qat_css_hdr {

	unsigned int module_type;

	unsigned int header_len;

	unsigned int header_ver;

	unsigned int module_id;

	unsigned int module_vendor;

	unsigned int date;

	unsigned int size;

	unsigned int key_size;

	unsigned int module_size;

	unsigned int exponent_size;

	unsigned int fw_type;

	unsigned int reserved[21];

};



struct icp_qat_simg_ae_mode {

	unsigned int     file_id;

	unsigned short   maj_ver;

	unsigned short   min_ver;

	unsigned int     dev_type;

	unsigned short   devmax_ver;

	unsigned short   devmin_ver;

	unsigned int     ae_mask;

	unsigned int     ctx_enables;

	char             fw_type;

	char             ctx_mode;

	char             nn_mode;

	char             lm0_mode;

	char             lm1_mode;

	char             scs_mode;

	char             lm2_mode;

	char             lm3_mode;

	char             tindex_mode;

	unsigned char    reserved[7];

	char             simg_name[256];

	char             appmeta_data[256];

};



struct icp_qat_suof_filehdr {

	unsigned int     file_id;

	unsigned int     check_sum;

	char             min_ver;

	char             maj_ver;

	char             fw_type;

	char             reserved;

	unsigned short   max_chunks;

	unsigned short   num_chunks;

};



struct icp_qat_suof_chunk_hdr {

	char chunk_id[ICP_QAT_SUOF_OBJ_ID_LEN];

	u64 offset;

	u64 size;

};



struct icp_qat_suof_strtable {

	unsigned int tab_length;

	unsigned int strings;

};



struct icp_qat_suof_objhdr {

	unsigned int img_length;

	unsigned int reserved;

};

#endif
 
#endif