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Commit b025e3aa authored by Vara Reddy's avatar Vara Reddy Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: move mdp transfer time node to drm modes. 



Each of the drm panel modes can set different mdp transfer time.
Move the node from panel dtsi to drm panel timing modes.

Change-Id: Ifd1a5fcf49420405531a8916c582ce96119d5457
Signed-off-by: default avatarVara Reddy <varar@codeaurora.org>
parent 72af9a4d

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+2 −2
Original line number Diff line number Diff line
@@ -640,8 +640,6 @@ Example: 
		qcom,mdss-dsi-mdp-trigger = <0>;

		qcom,mdss-dsi-dma-trigger = <0>;

		qcom,mdss-dsi-panel-framerate = <60>;

		qcom,mdss-dsi-panel-clockrate = <424000000>;

		qcom,mdss-mdp-transfer-time-us = <12500>;

		qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33

					22 27 1e 03 04 00];

                qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0
@@ -719,6 +717,8 @@ Example: 
				qcom,mdss-dsi-v-front-porch = <728>;

				qcom,mdss-dsi-v-pulse-width = <4>;

				qcom,mdss-dsi-panel-framerate = <60>;

				qcom,mdss-dsi-panel-clockrate = <424000000>;

				qcom,mdss-mdp-transfer-time-us = <12500>;

				qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00];

				qcom,mdss-dsi-t-clk-post = <0x02>;

				qcom,mdss-dsi-t-clk-pre = <0x2a>;

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+6 −3
Original line number Diff line number Diff line
@@ -372,6 +372,8 @@ struct dsi_panel_cmd_set { 
 * @v_sync_polarity:  Polarity of VSYNC (false is active low).

 * @refresh_rate:     Refresh rate in Hz.

 * @clk_rate_hz:      DSI bit clock rate per lane in Hz.

 * @mdp_transfer_time_us:   Specifies the mdp transfer time for command mode

 *                    panels in microseconds.

 * @dsc_enabled:      DSC compression enabled.

 * @dsc:              DSC compression configuration.

 * @roi_caps:         Panel ROI capabilities.
@@ -392,6 +394,7 @@ struct dsi_mode_info { 


	u32 refresh_rate;

	u64 clk_rate_hz;

	u32 mdp_transfer_time_us;

	bool dsc_enabled;

	struct msm_display_dsc_info *dsc;

	struct msm_roi_caps roi_caps;
@@ -484,15 +487,12 @@ struct dsi_video_engine_cfg { 
 * @wr_mem_continue:               DCS command for write_memory_continue.

 * @insert_dcs_command:            Insert DCS command as first byte of payload

 *                                 of the pixel data.

 * @mdp_transfer_time_us   Specifies the mdp transfer time for command mode

 *                         panels in microseconds

 */

struct dsi_cmd_engine_cfg {

	u32 max_cmd_packets_interleave;

	u32 wr_mem_start;

	u32 wr_mem_continue;

	bool insert_dcs_command;

	u32 mdp_transfer_time_us;

};



/**
@@ -529,6 +529,8 @@ struct dsi_host_config { 
 * @phy_timing_len:       Phy timing array length

 * @panel_jitter:         Panel jitter for RSC backoff

 * @panel_prefill_lines:  Panel prefill lines for RSC

 * @mdp_transfer_time_us:   Specifies the mdp transfer time for command mode

 *                          panels in microseconds.

 * @clk_rate_hz:          DSI bit clock per lane in hz.

 * @topology:             Topology selected for the panel

 * @dsc:                  DSC compression info
@@ -544,6 +546,7 @@ struct dsi_display_mode_priv_info { 
	u32 panel_jitter_numer;

	u32 panel_jitter_denom;

	u32 panel_prefill_lines;

	u32 mdp_transfer_time_us;

	u64 clk_rate_hz;



	struct msm_display_topology topology;

drivers/gpu/drm/msm/dsi-staging/dsi_drm.c

+3 −1
Original line number Diff line number Diff line
@@ -401,6 +401,8 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, 
	mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;

	mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;

	mode_info->clk_rate = dsi_mode.priv_info->clk_rate_hz;

	mode_info->mdp_transfer_time_us =

		dsi_mode.priv_info->mdp_transfer_time_us;



	memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,

			sizeof(struct msm_display_topology));
@@ -486,7 +488,7 @@ int dsi_conn_set_info_blob(struct drm_connector *connector, 
	case DSI_OP_CMD_MODE:

		sde_kms_info_add_keystr(info, "panel mode", "command");

		sde_kms_info_add_keyint(info, "mdp_transfer_time_us",

				panel->cmd_config.mdp_transfer_time_us);

				mode_info->mdp_transfer_time_us);

		sde_kms_info_add_keystr(info, "qsync support",

				panel->qsync_min_fps ? "true" : "false");

		break;

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+12 −8
Original line number Diff line number Diff line
@@ -737,9 +737,12 @@ static int dsi_panel_parse_timing(struct dsi_mode_info *mode, 
	int rc = 0;

	u64 tmp64 = 0;

	struct dsi_display_mode *display_mode;

	struct dsi_display_mode_priv_info *priv_info;



	display_mode = container_of(mode, struct dsi_display_mode, timing);



	priv_info = display_mode->priv_info;



	rc = utils->read_u64(utils->data,

			"qcom,mdss-dsi-panel-clockrate", &tmp64);

	if (rc == -EOVERFLOW) {
@@ -751,6 +754,15 @@ static int dsi_panel_parse_timing(struct dsi_mode_info *mode, 
	mode->clk_rate_hz = !rc ? tmp64 : 0;

	display_mode->priv_info->clk_rate_hz = mode->clk_rate_hz;



	rc = utils->read_u32(utils->data, "qcom,mdss-mdp-transfer-time-us",

				&mode->mdp_transfer_time_us);

	if (!rc)

		display_mode->priv_info->mdp_transfer_time_us =

			mode->mdp_transfer_time_us;

	else

		display_mode->priv_info->mdp_transfer_time_us =

			DEFAULT_MDP_TRANSFER_TIME;



	rc = utils->read_u32(utils->data,

				"qcom,mdss-dsi-panel-framerate",

				&mode->refresh_rate);
@@ -1342,14 +1354,6 @@ static int dsi_panel_parse_cmd_host_config(struct dsi_cmd_engine_cfg *cfg, 
		goto error;

	}



	if (utils->read_u32(utils->data, "qcom,mdss-mdp-transfer-time-us",

				&val)) {

		pr_debug("[%s] Fallback to default transfer-time-us\n", name);

		cfg->mdp_transfer_time_us = DEFAULT_MDP_TRANSFER_TIME;

	} else {

		cfg->mdp_transfer_time_us = val;

	}



error:

	return rc;

}

drivers/gpu/drm/msm/msm_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -444,6 +444,8 @@ struct msm_display_topology { 
 * @comp_info:       compression info supported

 * @roi_caps:        panel roi capabilities

 * @wide_bus_en:	wide-bus mode cfg for interface module

 * @mdp_transfer_time_us   Specifies the mdp transfer time for command mode

 *                         panels in microseconds.

 */

struct msm_mode_info {

	uint32_t frame_rate;
@@ -456,6 +458,7 @@ struct msm_mode_info { 
	struct msm_compression_info comp_info;

	struct msm_roi_caps roi_caps;

	bool wide_bus_en;

	u32 mdp_transfer_time_us;

};



/**