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Commit af6ff923 authored by Raviteja Tamatam's avatar Raviteja Tamatam
Browse files

ARM: dts: msm: add sde node for SM6150 target 



Add sde node for SM6150 target which will be used by
display driver.

Change-Id: I300615d49a1ac83ef817cea526975c4ae59f4878
Signed-off-by: default avatarRaviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent f6fbeafa

arch/arm64/boot/dts/qcom/sm6150-idp-overlay.dts

+4 −0
Original line number Diff line number Diff line
@@ -24,3 +24,7 @@ 
	qcom,msm-id = <355 0x0>;

	qcom,board-id = <34 0>;

};



&dsi_hx83112a_truly_vid_display {

	qcom,dsi-display-active;

};

arch/arm64/boot/dts/qcom/sm6150-idp.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
 */



#include <dt-bindings/iio/qcom,spmi-vadc.h>

#include "sm6150-sde-display.dtsi"



&soc {

};
@@ -114,3 +115,24 @@ 
	qcom,step-charging-enable;

	qcom,sw-jeita-enable;

};



&dsi_sim_cmd {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,platform-reset-gpio = <&tlmm 91 0>;

};



&dsi_sim_vid {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,platform-reset-gpio = <&tlmm 91 0>;

};



&dsi_hx83112a_truly_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <4095>;

	qcom,platform-te-gpio = <&tlmm 90 0>;

	qcom,platform-reset-gpio = <&tlmm 91 0>;

};

arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi

+56 −0
Original line number Diff line number Diff line
@@ -469,6 +469,62 @@ 
			};

		};



		pmx_sde: pmx_sde {

			sde_dsi_active: sde_dsi_active {

				mux {

					pins = "gpio91";

					function = "gpio";

				};



				config {

					pins = "gpio91";

					drive-strength = <8>;   /* 8 mA */

					bias-disable = <0>;   /* no pull */

				};

			};



			sde_dsi_suspend: sde_dsi_suspend {

				mux {

					pins = "gpio91";

					function = "gpio";

				};



				config {

					pins = "gpio91";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};

		};



		pmx_sde_te {

			sde_te_active: sde_te_active {

				mux {

					pins = "gpio90";

					function = "mdp_vsync";

				};



				config {

					pins = "gpio90";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			sde_te_suspend: sde_te_suspend {

				mux {

					pins = "gpio90";

					function = "mdp_vsync";

				};



				config {

					pins = "gpio90";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};

		};



		/* SDC pin type */

		sdc1_clk_on: sdc1_clk_on {

			config {

arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi

0 → 100644
+229 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "dsi-panel-sim-video.dtsi"

#include "dsi-panel-sim-cmd.dtsi"

#include "dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi"

#include <dt-bindings/clock/mdss-14nm-pll-clk.h>



&soc {

	dsi_panel_pwr_supply: dsi_panel_pwr_supply {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "lab";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

		};



		qcom,panel-supply-entry@2 {

			reg = <2>;

			qcom,supply-name = "ibb";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	dsi_sim_vid_display: qcom,dsi-display@0 {

		label = "dsi_sim_vid_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";



		qcom,dsi-panel = <&dsi_sim_vid>;

	};



	dsi_sim_cmd_display: qcom,dsi-display@1 {

		label = "dsi_sim_cmd_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";



		qcom,dsi-panel = <&dsi_sim_cmd>;

	};



	dsi_hx83112a_truly_vid_display: qcom,dsi-display@2 {

		label = "dsi_hx83112a_truly_vid_display";

		qcom,display-type = "primary";



		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";



		qcom,dsi-panel = <&dsi_hx83112a_truly_video>;

	};



	sde_dsi: qcom,dsi-display {

		compatible = "qcom,dsi-display";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;



		clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,

			 <&mdss_dsi0_pll PIX0_MUX_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0";

		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,platform-te-gpio = <&tlmm 90 0>;



		vddio-supply = <&pm6150_l13>;

		lab-supply = <&lcdb_ldo_vreg>;

		ibb-supply = <&lcdb_ncp_vreg>;



		qcom,dsi-display-list =

			<&dsi_sim_vid_display

			&dsi_sim_cmd_display

			&dsi_hx83112a_truly_vid_display>;

	};



	sde_wb: qcom,wb-display@0 {

		compatible = "qcom,wb-display";

		cell-index = <0>;

		label = "wb_display";

	};



	ext_disp: qcom,msm-ext-disp {

		compatible = "qcom,msm-ext-disp";



		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

			compatible = "qcom,msm-ext-disp-audio-codec-rx";

		};

	};

};



&mdss_mdp {

	connectors = <&sde_wb &sde_dsi>;

};



&dsi_sim_vid {

	qcom,mdss-dsi-display-timings {

		qcom,mdss-dsi-t-clk-post = <0x0e>;

		qcom,mdss-dsi-t-clk-pre = <0x31>;

		timing@0{

			qcom,mdss-dsi-panel-phy-timings =

				[24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1c 08 09 05 02 04 a0];



			qcom,display-topology = <1 0 1>,

						<2 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_sim_cmd {

	qcom,mdss-dsi-display-timings {

		qcom,mdss-dsi-t-clk-post = <0x0e>;

		qcom,mdss-dsi-t-clk-pre = <0x31>;

		timing@0{

			qcom,mdss-dsi-panel-phy-timings =

				[24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1c 08 09 05 02 04 a0];



			qcom,display-topology = <1 0 1>,

						<2 2 1>;

			qcom,default-topology-index = <1>;

			qcom,panel-roi-alignment = <720 40 720 40 720 40>;

			qcom,partial-update-enabled = "single_roi";

		};



		timing@1{

			qcom,mdss-dsi-panel-phy-timings =

				[24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1c 08 09 05 02 04 a0];

			qcom,display-topology = <1 0 1>,

						<2 2 1>;

			qcom,default-topology-index = <1>;

			qcom,panel-roi-alignment = <540 40 540 40 540 40>;

			qcom,partial-update-enabled = "single_roi";

		};



		timing@2{

			qcom,mdss-dsi-panel-phy-timings =

				[24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1c 08 09 05 02 04 a0];

			qcom,display-topology = <1 0 1>,

						<2 2 1>;

			qcom,default-topology-index = <1>;

			qcom,panel-roi-alignment = <360 40 360 40 360 40>;

			qcom,partial-update-enabled = "single_roi";

		};

	};

};



&dsi_hx83112a_truly_video {

	qcom,mdss-dsi-display-timings {

		qcom,mdss-dsi-t-clk-post = <0x0e>;

		qcom,mdss-dsi-t-clk-pre = <0x31>;

		timing@0{

			qcom,mdss-dsi-panel-phy-timings =

				[24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1f 08 09 05 02 04 a0

				24 1c 08 09 05 02 04 a0];



			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};

arch/arm64/boot/dts/qcom/sm6150-sde-pll.dtsi

0 → 100644
+64 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94400 {

		compatible = "qcom,mdss_dsi_pll_14nm";

		label = "MDSS DSI 0 PLL";

		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0xae94400 0x588>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "gdsc_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dp_pll: qcom,mdss_dp_pll@c011000 {

		status = "disabled";

		compatible = "qcom,mdss_dp_pll_7nm";

		label = "MDSS DP PLL";

		cell-index = <0>;

		#clock-cells = <1>;



		reg = <0x088ea000 0x200>,

		      <0x088eaa00 0x200>,

		      <0x088ea200 0x200>,

		      <0x088ea600 0x200>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk", "pipe_clk";

		clock-rate = <0>;

	};

};