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Commit af56ffa3 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: pcie: enable PCIe ASPM/PCI-PM by default without DT entry"

parents 3b156bc8 54c6a72a

Documentation/devicetree/bindings/pci/msm_pcie.txt

+8 −8
Original line number Original line Diff line number Diff line
@@ -63,10 +63,10 @@ Optional Properties: 
				"pcie_0_ldo";

				"pcie_0_ldo";

  - max-clock-frequency-hz: list of the maximum operating frequencies stored

  - max-clock-frequency-hz: list of the maximum operating frequencies stored

				in the same order of clock names;

				in the same order of clock names;

  - qcom,l0s-supported: L0s is supported.

  - qcom,no-l0s-supported: L0s is not supported.

  - qcom,l1-supported: L1 is supported.

  - qcom,no-l1-supported: L1 is not supported.

  - qcom,l1ss-supported: L1 sub-states (L1ss) is supported.

  - qcom,no-l1ss-supported: L1 sub-states (L1ss) is not supported.

  - qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to

  - qcom,no-aux-clk-sync: The AUX clock is not synchronous to the Core clock to

    support L1ss.

    support L1ss.

  - qcom,common-clk-en: Enables the common clock configuration for the endpoint.

  - qcom,common-clk-en: Enables the common clock configuration for the endpoint.

  - qcom,clk-power-manage-en: Enables the clock power management for the

  - qcom,clk-power-manage-en: Enables the clock power management for the
@@ -257,10 +257,10 @@ Example: 




		max-clock-frequency-hz = <125000000>, <0>, <1000000>,

		max-clock-frequency-hz = <125000000>, <0>, <1000000>,

						<0>, <0>, <0>, <0>;

						<0>, <0>, <0>, <0>;

		qcom,l0s-supported;

		qcom,no-l0s-supported;

		qcom,l1-supported;

		qcom,no-l1-supported;

		qcom,l1ss-supported;

		qcom,no-l1ss-supported;

		qcom,aux-clk-sync;

		qcom,no-aux-clk-sync;

		qcom,max-link-speed = <0x2>;

		qcom,max-link-speed = <0x2>;

		qcom,n-fts = <0x50>;

		qcom,n-fts = <0x50>;

		qcom,pcie-phy-ver = <1>;

		qcom,pcie-phy-ver = <1>;

drivers/pci/host/pci-msm.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -5783,24 +5783,24 @@ static int msm_pcie_probe(struct platform_device *pdev) 
	}

	}





	msm_pcie_dev[rc_idx].l0s_supported =

	msm_pcie_dev[rc_idx].l0s_supported =

		of_property_read_bool((&pdev->dev)->of_node,

		!of_property_read_bool((&pdev->dev)->of_node,

				"qcom,l0s-supported");

				"qcom,no-l0s-supported");

	if (msm_pcie_invert_l0s_support & BIT(rc_idx))

	if (msm_pcie_invert_l0s_support & BIT(rc_idx))

		msm_pcie_dev[rc_idx].l0s_supported =

		msm_pcie_dev[rc_idx].l0s_supported =

			!msm_pcie_dev[rc_idx].l0s_supported;

			!msm_pcie_dev[rc_idx].l0s_supported;

	PCIE_DBG(&msm_pcie_dev[rc_idx], "L0s is %s supported.\n",

	PCIE_DBG(&msm_pcie_dev[rc_idx], "L0s is %s supported.\n",

		msm_pcie_dev[rc_idx].l0s_supported ? "" : "not");

		msm_pcie_dev[rc_idx].l0s_supported ? "" : "not");

	msm_pcie_dev[rc_idx].l1_supported =

	msm_pcie_dev[rc_idx].l1_supported =

		of_property_read_bool((&pdev->dev)->of_node,

		!of_property_read_bool((&pdev->dev)->of_node,

				"qcom,l1-supported");

				"qcom,no-l1-supported");

	if (msm_pcie_invert_l1_support & BIT(rc_idx))

	if (msm_pcie_invert_l1_support & BIT(rc_idx))

		msm_pcie_dev[rc_idx].l1_supported =

		msm_pcie_dev[rc_idx].l1_supported =

			!msm_pcie_dev[rc_idx].l1_supported;

			!msm_pcie_dev[rc_idx].l1_supported;

	PCIE_DBG(&msm_pcie_dev[rc_idx], "L1 is %s supported.\n",

	PCIE_DBG(&msm_pcie_dev[rc_idx], "L1 is %s supported.\n",

		msm_pcie_dev[rc_idx].l1_supported ? "" : "not");

		msm_pcie_dev[rc_idx].l1_supported ? "" : "not");

	msm_pcie_dev[rc_idx].l1ss_supported =

	msm_pcie_dev[rc_idx].l1ss_supported =

		of_property_read_bool((&pdev->dev)->of_node,

		!of_property_read_bool((&pdev->dev)->of_node,

				"qcom,l1ss-supported");

				"qcom,no-l1ss-supported");

	if (msm_pcie_invert_l1ss_support & BIT(rc_idx))

	if (msm_pcie_invert_l1ss_support & BIT(rc_idx))

		msm_pcie_dev[rc_idx].l1ss_supported =

		msm_pcie_dev[rc_idx].l1ss_supported =

			!msm_pcie_dev[rc_idx].l1ss_supported;

			!msm_pcie_dev[rc_idx].l1ss_supported;
@@ -5818,8 +5818,8 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		"Clock power management is %s enabled.\n",

		"Clock power management is %s enabled.\n",

		msm_pcie_dev[rc_idx].clk_power_manage_en ? "" : "not");

		msm_pcie_dev[rc_idx].clk_power_manage_en ? "" : "not");

	msm_pcie_dev[rc_idx].aux_clk_sync =

	msm_pcie_dev[rc_idx].aux_clk_sync =

		of_property_read_bool((&pdev->dev)->of_node,

		!of_property_read_bool((&pdev->dev)->of_node,

				"qcom,aux-clk-sync");

				"qcom,no-aux-clk-sync");

	PCIE_DBG(&msm_pcie_dev[rc_idx],

	PCIE_DBG(&msm_pcie_dev[rc_idx],

		"AUX clock is %s synchronous to Core clock.\n",

		"AUX clock is %s synchronous to Core clock.\n",

		msm_pcie_dev[rc_idx].aux_clk_sync ? "" : "not");

		msm_pcie_dev[rc_idx].aux_clk_sync ? "" : "not");