Loading arch/powerpc/kernel/legacy_serial.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -37,7 +37,7 @@ static int legacy_serial_console = -1; static int __init add_legacy_port(struct device_node *np, int want_index, static int __init add_legacy_port(struct device_node *np, int want_index, int iotype, phys_addr_t base, int iotype, phys_addr_t base, phys_addr_t taddr, unsigned long irq, phys_addr_t taddr, unsigned long irq, unsigned int flags) upf_t flags) { { u32 *clk, *spd, clock = BASE_BAUD * 16; u32 *clk, *spd, clock = BASE_BAUD * 16; int index; int index; Loading Loading @@ -113,7 +113,7 @@ static int __init add_legacy_soc_port(struct device_node *np, { { phys_addr_t addr; phys_addr_t addr; u32 *addrp; u32 *addrp; unsigned int flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; /* We only support ports that have a clock frequency properly /* We only support ports that have a clock frequency properly * encoded in the device-tree. * encoded in the device-tree. Loading arch/powerpc/kernel/nvram_64.c +2 −1 Original line number Original line Diff line number Diff line Loading @@ -174,9 +174,10 @@ static int dev_nvram_ioctl(struct inode *inode, struct file *file, return 0; return 0; } } #endif /* CONFIG_PPC_PMAC */ #endif /* CONFIG_PPC_PMAC */ } default: return -EINVAL; return -EINVAL; } } } struct file_operations nvram_fops = { struct file_operations nvram_fops = { .owner = THIS_MODULE, .owner = THIS_MODULE, Loading arch/powerpc/kernel/process.c +5 −1 Original line number Original line Diff line number Diff line Loading @@ -362,7 +362,11 @@ static void show_instructions(struct pt_regs *regs) if (!(i % 8)) if (!(i % 8)) printk("\n"); printk("\n"); if (BAD_PC(pc) || __get_user(instr, (unsigned int *)pc)) { /* We use __get_user here *only* to avoid an OOPS on a * bad address because the pc *should* only be a * kernel address. */ if (BAD_PC(pc) || __get_user(instr, (unsigned int __user *)pc)) { printk("XXXXXXXX "); printk("XXXXXXXX "); } else { } else { if (regs->nip == pc) if (regs->nip == pc) Loading arch/powerpc/kernel/setup_32.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -111,7 +111,7 @@ unsigned long __init early_init(unsigned long dt_ptr) /* First zero the BSS -- use memset_io, some platforms don't have /* First zero the BSS -- use memset_io, some platforms don't have * caches on yet */ * caches on yet */ memset_io(PTRRELOC(&__bss_start), 0, _end - __bss_start); memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, _end - __bss_start); /* /* * Identify the CPU type and fix up code sections * Identify the CPU type and fix up code sections Loading arch/powerpc/lib/sstep.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -18,7 +18,7 @@ extern char system_call_common[]; #ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64 /* Bits in SRR1 that are copied from MSR */ /* Bits in SRR1 that are copied from MSR */ #define MSR_MASK 0xffffffff87c0ffff #define MSR_MASK 0xffffffff87c0ffffUL #else #else #define MSR_MASK 0x87c0ffff #define MSR_MASK 0x87c0ffff #endif #endif Loading Loading
arch/powerpc/kernel/legacy_serial.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -37,7 +37,7 @@ static int legacy_serial_console = -1; static int __init add_legacy_port(struct device_node *np, int want_index, static int __init add_legacy_port(struct device_node *np, int want_index, int iotype, phys_addr_t base, int iotype, phys_addr_t base, phys_addr_t taddr, unsigned long irq, phys_addr_t taddr, unsigned long irq, unsigned int flags) upf_t flags) { { u32 *clk, *spd, clock = BASE_BAUD * 16; u32 *clk, *spd, clock = BASE_BAUD * 16; int index; int index; Loading Loading @@ -113,7 +113,7 @@ static int __init add_legacy_soc_port(struct device_node *np, { { phys_addr_t addr; phys_addr_t addr; u32 *addrp; u32 *addrp; unsigned int flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; /* We only support ports that have a clock frequency properly /* We only support ports that have a clock frequency properly * encoded in the device-tree. * encoded in the device-tree. Loading
arch/powerpc/kernel/nvram_64.c +2 −1 Original line number Original line Diff line number Diff line Loading @@ -174,9 +174,10 @@ static int dev_nvram_ioctl(struct inode *inode, struct file *file, return 0; return 0; } } #endif /* CONFIG_PPC_PMAC */ #endif /* CONFIG_PPC_PMAC */ } default: return -EINVAL; return -EINVAL; } } } struct file_operations nvram_fops = { struct file_operations nvram_fops = { .owner = THIS_MODULE, .owner = THIS_MODULE, Loading
arch/powerpc/kernel/process.c +5 −1 Original line number Original line Diff line number Diff line Loading @@ -362,7 +362,11 @@ static void show_instructions(struct pt_regs *regs) if (!(i % 8)) if (!(i % 8)) printk("\n"); printk("\n"); if (BAD_PC(pc) || __get_user(instr, (unsigned int *)pc)) { /* We use __get_user here *only* to avoid an OOPS on a * bad address because the pc *should* only be a * kernel address. */ if (BAD_PC(pc) || __get_user(instr, (unsigned int __user *)pc)) { printk("XXXXXXXX "); printk("XXXXXXXX "); } else { } else { if (regs->nip == pc) if (regs->nip == pc) Loading
arch/powerpc/kernel/setup_32.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -111,7 +111,7 @@ unsigned long __init early_init(unsigned long dt_ptr) /* First zero the BSS -- use memset_io, some platforms don't have /* First zero the BSS -- use memset_io, some platforms don't have * caches on yet */ * caches on yet */ memset_io(PTRRELOC(&__bss_start), 0, _end - __bss_start); memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, _end - __bss_start); /* /* * Identify the CPU type and fix up code sections * Identify the CPU type and fix up code sections Loading
arch/powerpc/lib/sstep.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -18,7 +18,7 @@ extern char system_call_common[]; #ifdef CONFIG_PPC64 #ifdef CONFIG_PPC64 /* Bits in SRR1 that are copied from MSR */ /* Bits in SRR1 that are copied from MSR */ #define MSR_MASK 0xffffffff87c0ffff #define MSR_MASK 0xffffffff87c0ffffUL #else #else #define MSR_MASK 0x87c0ffff #define MSR_MASK 0x87c0ffff #endif #endif Loading