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Commit aea812e1 authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: tegra: add pll_x freq table entry for 750MHz 



Some SKUs limit the maximum CPU frequency to 750MHz; see
tegra2_pllx_clk_init(). The pll_x frequency table needs an entry for this
frequency, or there will be continual log spam from the cpufreq driver
attempting to set this rate, yet there being no table entry for it.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 00341028

arch/arm/mach-tegra/tegra2_clocks.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -1764,6 +1764,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { 
	{ 19200000, 760000000,  950,  24, 1, 8},

	{ 19200000, 760000000,  950,  24, 1, 8},

	{ 26000000, 760000000,  760,  26, 1, 12},

	{ 26000000, 760000000,  760,  26, 1, 12},





	/* 750 MHz */

	{ 12000000, 750000000,  750,  12, 1, 12},

	{ 13000000, 750000000,  750,  13, 1, 12},

	{ 19200000, 750000000,  625,  16, 1, 8},

	{ 26000000, 750000000,  750,  26, 1, 12},



	/* 608 MHz */

	/* 608 MHz */

	{ 12000000, 608000000,  608,  12, 1, 12},

	{ 12000000, 608000000,  608,  12, 1, 12},

	{ 13000000, 608000000,  608,  13, 1, 12},

	{ 13000000, 608000000,  608,  13, 1, 12},