Loading Documentation/devicetree/bindings/usb/dwc3.txt +2 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,8 @@ Optional properties: from P0 to P1/P2/P3 without delay. - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check during HS transmit. - snps,ssp-u3-u0-quirk: when set, core always changes PHY power state to P2, before attempting a U3 exit handshake. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold Loading drivers/usb/dwc3/core.c +6 −0 Original line number Diff line number Diff line Loading @@ -546,6 +546,10 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_del_phy_power_chg_quirk) reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; if (dwc->ssp_u3_u0_quirk) reg |= (DWC3_GUSB3PIPECTL_UX_EXIT_PX | DWC3_GUSB3PIPECTL_P3EXSIGP2); dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); Loading Loading @@ -1039,6 +1043,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); dwc->ssp_u3_u0_quirk = device_property_read_bool(dev, "snps,ssp-u3-u0-quirk"); device_property_read_u8(dev, "snps,tx_de_emphasis", &tx_de_emphasis); device_property_read_string(dev, "snps,hsphy_interface", Loading drivers/usb/dwc3/core.h +2 −0 Original line number Diff line number Diff line Loading @@ -253,6 +253,7 @@ #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) #define DWC3_GUSB3PIPECTL_P3EXSIGP2 BIT(10) #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) Loading Loading @@ -1121,6 +1122,7 @@ struct dwc3 { unsigned dis_tx_ipgap_linecheck_quirk:1; unsigned tx_de_emphasis_quirk:1; unsigned ssp_u3_u0_quirk:1; unsigned tx_de_emphasis:2; unsigned err_evt_seen:1; unsigned enable_bus_suspend:1; Loading Loading
Documentation/devicetree/bindings/usb/dwc3.txt +2 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,8 @@ Optional properties: from P0 to P1/P2/P3 without delay. - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check during HS transmit. - snps,ssp-u3-u0-quirk: when set, core always changes PHY power state to P2, before attempting a U3 exit handshake. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold Loading
drivers/usb/dwc3/core.c +6 −0 Original line number Diff line number Diff line Loading @@ -546,6 +546,10 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_del_phy_power_chg_quirk) reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; if (dwc->ssp_u3_u0_quirk) reg |= (DWC3_GUSB3PIPECTL_UX_EXIT_PX | DWC3_GUSB3PIPECTL_P3EXSIGP2); dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); Loading Loading @@ -1039,6 +1043,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); dwc->ssp_u3_u0_quirk = device_property_read_bool(dev, "snps,ssp-u3-u0-quirk"); device_property_read_u8(dev, "snps,tx_de_emphasis", &tx_de_emphasis); device_property_read_string(dev, "snps,hsphy_interface", Loading
drivers/usb/dwc3/core.h +2 −0 Original line number Diff line number Diff line Loading @@ -253,6 +253,7 @@ #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) #define DWC3_GUSB3PIPECTL_P3EXSIGP2 BIT(10) #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) Loading Loading @@ -1121,6 +1122,7 @@ struct dwc3 { unsigned dis_tx_ipgap_linecheck_quirk:1; unsigned tx_de_emphasis_quirk:1; unsigned ssp_u3_u0_quirk:1; unsigned tx_de_emphasis:2; unsigned err_evt_seen:1; unsigned enable_bus_suspend:1; Loading