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Commit ae0cd96e authored by Steve Cohen's avatar Steve Cohen
Browse files

drm/msm/sde: register DSC_CTL and MERGE_3D blocks for debug dump 



Add new hw blocks to the debug dump list so these register
values get dumped for debug analysis.  Also fix the block
length calculation during reg dump to prevent possibility
of accessing registers outside the specified max range.

Change-Id: Iee9adbe5bf0d54a2cbe7d433cc96705060353eeb
Signed-off-by: default avatarSteve Cohen <cohens@codeaurora.org>
parent 0bb81cfe

drivers/gpu/drm/msm/sde/sde_hw_dsc.c

+11 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#define DSC_RANGE_MAX_QP                0x0B0

#define DSC_RANGE_BPG_OFFSET            0x0EC



#define DSC_CTL_BLOCK_SIZE              0x300

#define DSC_CTL(m)     \

	(((m == DSC_NONE) || (m >= DSC_MAX)) ? 0 : (0x1800 - 0x3FC * (m - 1)))
@@ -239,6 +240,7 @@ struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx, 
{

	struct sde_hw_dsc *c;

	struct sde_dsc_cfg *cfg;

	u32 dsc_ctl_offset;

	int rc;



	c = kzalloc(sizeof(*c), GFP_KERNEL);
@@ -264,6 +266,15 @@ struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx, 
	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,

		c->hw.blk_off + c->hw.length, c->hw.xin_id);



	if ((c->idx == DSC_0) &&

			test_bit(SDE_DSC_OUTPUT_CTRL, &cfg->features)) {

		dsc_ctl_offset = DSC_CTL(c->idx);

		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "dsc_ctl",

			c->hw.blk_off + dsc_ctl_offset,

			c->hw.blk_off + dsc_ctl_offset + DSC_CTL_BLOCK_SIZE,

			c->hw.xin_id);

	}



	return c;



blk_init_error:

drivers/gpu/drm/msm/sde/sde_hw_pingpong.c

+8 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ static struct sde_hw_merge_3d *_sde_pp_merge_3d_init(enum sde_merge_3d idx, 
{

	struct sde_hw_merge_3d *c;

	struct sde_merge_3d_cfg *cfg;

	static u32 merge3d_init_mask;



	if (idx < MERGE_3D_0)

		return NULL;
@@ -131,6 +132,13 @@ static struct sde_hw_merge_3d *_sde_pp_merge_3d_init(enum sde_merge_3d idx, 
	c->caps = cfg;

	_setup_merge_3d_ops(&c->ops, c->caps);



	if (!(merge3d_init_mask & BIT(idx))) {

		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,

				c->hw.blk_off, c->hw.blk_off + c->hw.length,

				c->hw.xin_id);

		merge3d_init_mask |= BIT(idx);

	}



	return c;

}

drivers/gpu/drm/msm/sde_dbg.c

+6 −5
Original line number Diff line number Diff line
@@ -3495,11 +3495,12 @@ static u32 _sde_dbg_get_dump_range(struct sde_dbg_reg_offset *range_node, 
{

	u32 length = 0;



	if ((range_node->start > range_node->end) ||

		(range_node->end > max_offset) || (range_node->start == 0

		&& range_node->end == 0)) {

	if (range_node->start == 0 && range_node->end == 0) {

		length = max_offset;

	} else {

	} else if (range_node->start < max_offset) {

		if (range_node->end > max_offset)

			length = max_offset - range_node->start;

		else if (range_node->start < range_node->end)

			length = range_node->end - range_node->start;

	}