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Commit adafdc6f authored by Mika Kahola's avatar Mika Kahola Committed by Daniel Vetter
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drm/i915: Store max dotclock 



Store max dotclock into dev_priv structure so we are able
to filter out the modes that are not supported by our
platforms.

V2:
- limit the max dot clock frequency to max CD clock frequency
  for the gen9 and above
- limit the max dot clock frequency to 90% of the max CD clock
  frequency for the older gens
- for Cherryview the max dot clock frequency is limited to 95%
  of the max CD clock frequency
- for gen2 and gen3 the max dot clock limit is set to 90% of the
  2X max CD clock frequency

V3:
- max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
- in intel_compute_max_dotclk() the rounding method changed from
  round up to round down when computing max dotclock

V4:
- Haswell and Broadwell supports now dot clocks up to max CD clock
  frequency

Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 65d64cc5

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1792,6 +1792,7 @@ struct drm_i915_private { 
	unsigned int fsb_freq, mem_freq, is_ddr3;

	unsigned int skl_boot_cdclk;

	unsigned int cdclk_freq, max_cdclk_freq;

	unsigned int max_dotclk_freq;

	unsigned int hpll_freq;



	/**

drivers/gpu/drm/i915/intel_display.c

+20 −0
Original line number Diff line number Diff line
@@ -5240,6 +5240,21 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) 
			modeset_put_power_domains(dev_priv, put_domains[i]);

}



static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)

{

	int max_cdclk_freq = dev_priv->max_cdclk_freq;



	if (INTEL_INFO(dev_priv)->gen >= 9 ||

	    IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		return max_cdclk_freq;

	else if (IS_CHERRYVIEW(dev_priv))

		return max_cdclk_freq*95/100;

	else if (INTEL_INFO(dev_priv)->gen < 4)

		return 2*max_cdclk_freq*90/100;

	else

		return max_cdclk_freq*90/100;

}



static void intel_update_max_cdclk(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5279,8 +5294,13 @@ static void intel_update_max_cdclk(struct drm_device *dev) 
		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;

	}



	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);



	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",

			 dev_priv->max_cdclk_freq);



	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",

			 dev_priv->max_dotclk_freq);

}



static void intel_update_cdclk(struct drm_device *dev)