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Commit ad68f8d3 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: JZ4740: define IRQ numbers based on number of intc IRQs 



For interrupts numbered after those of the interrupt controller, define
their numbers based upon the number of interrupts provided by the SoC
interrupt controller. This is in preparation for supporting newer
Ingenic SoCs which provide more interrupts.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10143/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 943d69c6

arch/mips/include/asm/mach-jz4740/irq.h

+7 −3
Original line number Diff line number Diff line
@@ -19,6 +19,10 @@ 
#define MIPS_CPU_IRQ_BASE 0

#define JZ4740_IRQ_BASE 8



#ifdef CONFIG_MACH_JZ4740

# define NR_INTC_IRQS	32

#endif



/* 1st-level interrupts */

#define JZ4740_IRQ(x)		(JZ4740_IRQ_BASE + (x))

#define JZ4740_IRQ_I2C		JZ4740_IRQ(1)
@@ -45,12 +49,12 @@ 
#define JZ4740_IRQ_LCD		JZ4740_IRQ(30)



/* 2nd-level interrupts */

#define JZ4740_IRQ_DMA(x)	(JZ4740_IRQ(32) + (x))

#define JZ4740_IRQ_DMA(x)	(JZ4740_IRQ(NR_INTC_IRQS) + (x))



#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))

#define JZ4740_IRQ_GPIO(x)	(JZ4740_IRQ(48) + (x))

#define JZ4740_IRQ_GPIO(x)	(JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))



#define JZ4740_IRQ_ADC_BASE	JZ4740_IRQ(176)

#define JZ4740_IRQ_ADC_BASE	JZ4740_IRQ(NR_INTC_IRQS + 144)



#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)