Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit acea6f95 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv 



BDW has the same requirement but the w/a database doens't list
this w/a for BDW. Seems to be another one of those "stick a bunch
of known workarounds into this bag and write something on the label"
type of things.

Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 232ce337

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -5389,6 +5389,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_FF_THREAD_MODE,

		   I915_READ(GEN7_FF_THREAD_MODE) &

		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));



	/* WaDisableSemaphoreAndSyncFlipWait:chv */

	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,

		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

}



static void g4x_init_clock_gating(struct drm_device *dev)