Merge "ARM: config: Enable MMC related configs for qcs405" (acaed560) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm/configs/qcs405-perf_defconfig

+4 −0

Original line number	Diff line number	Diff line
		@@ -302,11 +302,15 @@ CONFIG_DUAL_ROLE_USB_INTF=y
		CONFIG_USB_GADGET=y
		CONFIG_USB_GADGET_VBUS_DRAW=500
		CONFIG_MMC=y
		CONFIG_MMC_PERF_PROFILING=y
		CONFIG_MMC_BLOCK_MINORS=32
		CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
		CONFIG_MMC_TEST=m
		CONFIG_MMC_PARANOID_SD_INIT=y
		CONFIG_MMC_CLKGATE=y
		CONFIG_MMC_SDHCI=y
		CONFIG_MMC_SDHCI_PLTFM=y
		CONFIG_MMC_SDHCI_MSM=y
		CONFIG_RTC_CLASS=y
		CONFIG_DMADEVICES=y
		CONFIG_UIO=y

arch/arm/configs/qcs405_defconfig

+5 −0

Original line number	Diff line number	Diff line
		@@ -318,11 +318,16 @@ CONFIG_USB_CONFIGFS=y
		CONFIG_USB_CONFIGFS_F_FS=y
		CONFIG_USB_CONFIGFS_F_DIAG=y
		CONFIG_MMC=y
		CONFIG_MMC_PERF_PROFILING=y
		CONFIG_MMC_BLOCK_MINORS=32
		CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
		CONFIG_MMC_TEST=m
		CONFIG_MMC_RING_BUFFER=y
		CONFIG_MMC_PARANOID_SD_INIT=y
		CONFIG_MMC_CLKGATE=y
		CONFIG_MMC_SDHCI=y
		CONFIG_MMC_SDHCI_PLTFM=y
		CONFIG_MMC_SDHCI_MSM=y
		CONFIG_RTC_CLASS=y
		CONFIG_DMADEVICES=y
		CONFIG_UIO=y

arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi

+138 −0

Original line number	Diff line number	Diff line
		@@ -643,5 +643,143 @@
		};
		};
		};

		/* SDC pin type */
		sdc1_clk_on: sdc1_clk_on {
		config {
		pins = "sdc1_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc1_clk_off: sdc1_clk_off {
		config {
		pins = "sdc1_clk";
		bias-disable; /* NO pull */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc1_cmd_on: sdc1_cmd_on {
		config {
		pins = "sdc1_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc1_cmd_off: sdc1_cmd_off {
		config {
		pins = "sdc1_cmd";
		num-grp-pins = <1>;
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc1_data_on: sdc1_data_on {
		config {
		pins = "sdc1_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc1_data_off: sdc1_data_off {
		config {
		pins = "sdc1_data";
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc1_rclk_on: sdc1_rclk_on {
		config {
		pins = "sdc1_rclk";
		bias-pull-down; /* pull down */
		};
		};

		sdc1_rclk_off: sdc1_rclk_off {
		config {
		pins = "sdc1_rclk";
		bias-pull-down; /* pull down */
		};
		};

		sdc2_clk_on: sdc2_clk_on {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc2_clk_off: sdc2_clk_off {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc2_cmd_on: sdc2_cmd_on {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_cmd_off: sdc2_cmd_off {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc2_data_on: sdc2_data_on {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_data_off: sdc2_data_off {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc2_cd_on: cd_on {
		mux {
		pins = "gpio21"; /* sdcard_det */
		function = "gpio";
		};

		config {
		pins = "gpio21";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		sdc2_cd_off: cd_off {
		mux {
		pins = "gpio21";
		function = "gpio";
		};

		config {
		pins = "gpio21";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};
		};

arch/arm64/boot/dts/qcom/qcs405-rumi.dtsi

+34 −0

Original line number	Diff line number	Diff line
		@@ -82,3 +82,37 @@
		};

		#include "qcs405-stub-regulator.dtsi"

		&sdhc_1 {
		/* VDD external regulator is enabled/disabled by pms405_l6 */
		vdd-io-supply = <&pms405_l6>;
		qcom,vdd-io-always-on;
		qcom,vdd-io-lpm-sup;
		qcom,vdd-io-voltage-level = <1704000 1800000>;
		qcom,vdd-io-current-level = <0 325000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
		pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;

		qcom,clk-rates = <400000 20000000 25000000 50000000>;
		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";

		status = "ok";
		};

		&sdhc_2 {
		/* VDD is an external regulator eLDO5 */
		vdd-io-supply = <&pms405_l11>;
		qcom,vdd-io-voltage-level = <2696000 3304000>;
		qcom,vdd-io-current-level = <0 22000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
		pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;

		qcom,clk-rates = <400000 20000000 25000000 50000000>;
		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";

		status = "disabled";
		};

arch/arm64/boot/dts/qcom/qcs405.dtsi

+54 −1

Original line number	Diff line number	Diff line
		@@ -40,7 +40,10 @@
		};
		};

		aliases { };
		aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
		};

		soc: soc { };

		@@ -540,6 +543,56 @@
		snps,hird-threshold = /bits/ 8 <0x10>;
		};
		};

		sdhc_1: sdhci@7804000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
		reg-names = "hc_mem", "cmdq_mem";

		interrupts = <0 123 0>, <0 138 0>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <8>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
		192000000 384000000>;
		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

		qcom,devfreq,freq-table = <50000000 200000000>;

		clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
		<&clock_gcc GCC_SDCC1_APPS_CLK>;
		clock-names = "iface_clk", "core_clk";

		qcom,nonremovable;
		status = "disabled";
		};

		sdhc_2: sdhci@7844000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x7844000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <0 125 0>, <0 221 0>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <4>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000
		50000000 100000000 201500000>;
		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
		"SDR104";

		qcom,devfreq,freq-table = <50000000 201500000>;

		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
		<&clock_gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface_clk", "core_clk";

		status = "disabled";
		};
		};

		#include "qcs405-gdsc.dtsi"