Commit ac8616e4 authored Feb 14, 2017 by Chen-Yu Tsai Committed by Maxime Ripard Mar 06, 2017

clk: sunxi-ng: mp: Adjust parent rate for pre-dividers



The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.

This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.

Cc: stable@vger.kernel.org
Fixes: 2ab836db ("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent c1ae3cfa

drivers/clk/sunxi-ng/ccu_mp.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -85,6 +85,10 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
		unsigned int m, p;
		u32 reg;

		/* Adjust parent_rate according to pre-dividers */
		ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
		-1, &parent_rate);

		reg = readl(cmp->common.base + cmp->common.reg);

		m = reg >> cmp->m.shift;
		@@ -117,6 +121,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned int m, p;
		u32 reg;

		/* Adjust parent_rate according to pre-dividers */
		ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
		-1, &parent_rate);

		max_m = cmp->m.max ?: 1 << cmp->m.width;
		max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);