Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ac149698 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: Fix BC1{EQ,NE}Z return offset calculation 



The conditions for branching when emulating the BC1EQZ & BC1NEZ
instructions were backwards, leading to each of those instructions being
treated as the other. Fix this by reversing the conditions, and clear up
the code a little for readability & checkpatch.

Fixes: c8a34581 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions")
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13151/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 93583e17

arch/mips/kernel/branch.c

+3 −15
Original line number Diff line number Diff line
@@ -688,21 +688,9 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, 
			}

			lose_fpu(1);    /* Save FPU state for the emulator. */

			reg = insn.i_format.rt;

			bit = 0;

			switch (insn.i_format.rs) {

			case bc1eqz_op:

				/* Test bit 0 */

				if (get_fpr32(&current->thread.fpu.fpr[reg], 0)

				    & 0x1)

					bit = 1;

				break;

			case bc1nez_op:

				/* Test bit 0 */

				if (!(get_fpr32(&current->thread.fpu.fpr[reg], 0)

				      & 0x1))

					bit = 1;

				break;

			}

			bit = get_fpr32(&current->thread.fpu.fpr[reg], 0) & 0x1;

			if (insn.i_format.rs == bc1eqz_op)

				bit = !bit;

			own_fpu(1);

			if (bit)

				epc = epc + 4 +