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Commit ac01bb7e authored by Kishore Y's avatar Kishore Y Committed by Tomi Valkeinen
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OMAP3630: DSS2: Updating MAX divider value 



In DPLL4 M3, M4, M5 and M6 field width has been increased by 1 bit in 3630.
So the max divider value that can be achived will be 32 and not 16.
In 3630 the functional clock is x1 of DPLL4 and not x2. Hence multiplier 2
is removed.

Signed-off-by: default avatarSudeep Basavaraj <sudeep.basavaraj@ti.com>
Signed-off-by: default avatarMukund Mittal <mmittal@ti.com>
Signed-off-by: default avatarKishore Y <kishore.y@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@nokia.com>
parent 2c59ff55

drivers/video/omap2/dss/dss.c

+19 −5
Original line number Original line Diff line number Diff line
@@ -223,6 +223,12 @@ void dss_dump_clocks(struct seq_file *s) 




	seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);

	seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);





	if (cpu_is_omap3630())

		seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",

			dpll4_ck_rate,

			dpll4_ck_rate / dpll4_m4_ck_rate,

			dss_clk_get_rate(DSS_CLK_FCK1));

	else

		seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",

		seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",

			dpll4_ck_rate,

			dpll4_ck_rate,

			dpll4_ck_rate / dpll4_m4_ck_rate,

			dpll4_ck_rate / dpll4_m4_ck_rate,
@@ -293,7 +299,8 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo) 
{

{

	unsigned long prate;

	unsigned long prate;





	if (cinfo->fck_div > 16 || cinfo->fck_div == 0)

	if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||

						cinfo->fck_div == 0)

		return -EINVAL;

		return -EINVAL;





	prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));

	prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
@@ -329,6 +336,9 @@ int dss_get_clock_div(struct dss_clock_info *cinfo) 
	if (cpu_is_omap34xx()) {

	if (cpu_is_omap34xx()) {

		unsigned long prate;

		unsigned long prate;

		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));

		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));

		if (cpu_is_omap3630())

			cinfo->fck_div = prate / (cinfo->fck);

		else

			cinfo->fck_div = prate / (cinfo->fck / 2);

			cinfo->fck_div = prate / (cinfo->fck / 2);

	} else {

	} else {

		cinfo->fck_div = 0;

		cinfo->fck_div = 0;
@@ -402,9 +412,13 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck, 




		goto found;

		goto found;

	} else if (cpu_is_omap34xx()) {

	} else if (cpu_is_omap34xx()) {

		for (fck_div = 16; fck_div > 0; --fck_div) {

		for (fck_div = (cpu_is_omap3630() ? 32 : 16);

					fck_div > 0; --fck_div) {

			struct dispc_clock_info cur_dispc;

			struct dispc_clock_info cur_dispc;





			if (cpu_is_omap3630())

				fck = prate / fck_div;

			else

				fck = prate / fck_div * 2;

				fck = prate / fck_div * 2;





			if (fck > DISPC_MAX_FCK)

			if (fck > DISPC_MAX_FCK)