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Commit ab7cfb55 authored by Paul Mundt's avatar Paul Mundt
Browse files

serial: sh-sci: Kill off bitrotted H8/300 support. 



h8300 has never been updated upstream to support the conversion to the
driver model (which happened mid-2.5), and it doesn't seem likely that it
ever will. Kill off the remaining bitrotted support to reduce the
maintenance burden going forward.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 0792644d

drivers/tty/serial/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -974,7 +974,7 @@ config SERIAL_IP22_ZILOG_CONSOLE 


config SERIAL_SH_SCI

	tristate "SuperH SCI(F) serial port support"

	depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE)

	depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)

	select SERIAL_CORE



config SERIAL_SH_SCI_NR_UARTS

drivers/tty/serial/sh-sci.c

+2 −28
Original line number Diff line number Diff line
@@ -54,10 +54,6 @@ 
#include <asm/sh_bios.h>

#endif



#ifdef CONFIG_H8300

#include <asm/gpio.h>

#endif



#include "sh-sci.h"



struct sci_port {
@@ -164,23 +160,7 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c) 
}

#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */



#if defined(__H8300H__) || defined(__H8300S__)

static void sci_init_pins(struct uart_port *port, unsigned int cflag)

{

	int ch = (port->mapbase - SMR0) >> 3;



	/* set DDR regs */

	H8300_GPIO_DDR(h8300_sci_pins[ch].port,

		       h8300_sci_pins[ch].rx,

		       H8300_GPIO_INPUT);

	H8300_GPIO_DDR(h8300_sci_pins[ch].port,

		       h8300_sci_pins[ch].tx,

		       H8300_GPIO_OUTPUT);



	/* tx mark output*/

	H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;

}

#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)

#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)

static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)

{

	if (port->mapbase == 0xA4400000) {
@@ -1863,14 +1843,8 @@ static int __devinit serial_console_setup(struct console *co, char *options) 
	if (options)

		uart_parse_options(options, &baud, &parity, &bits, &flow);



	ret = uart_set_options(port, co, baud, parity, bits, flow);

#if defined(__H8300H__) || defined(__H8300S__)

	/* disable rx interrupt */

	if (ret == 0)

		sci_stop_rx(port);

#endif

	/* TODO: disable clock */

	return ret;

	return uart_set_options(port, co, baud, parity, bits, flow);

}



static struct console serial_console = {

drivers/tty/serial/sh-sci.h

+11 −92
Original line number Diff line number Diff line
@@ -2,13 +2,6 @@ 
#include <linux/io.h>

#include <linux/gpio.h>



#if defined(CONFIG_H83007) || defined(CONFIG_H83068)

#include <asm/regs306x.h>

#endif

#if defined(CONFIG_H8S2678)

#include <asm/regs267x.h>

#endif



#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \

    defined(CONFIG_CPU_SUBTYPE_SH7707) || \

    defined(CONFIG_CPU_SUBTYPE_SH7708) || \
@@ -72,10 +65,6 @@ 
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)

# define SCSPTR2 0xffe80020 /* 16 bit SCIF */

# define SCIF_ORER 0x0001   /* overrun error bit */

#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)

# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)

#elif defined(CONFIG_H8S2678)

# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)

#elif defined(CONFIG_CPU_SUBTYPE_SH7757)

# define SCSPTR0 0xfe4b0020

# define SCIF_ORER 0x0001
@@ -223,17 +212,6 @@ 
    }									\

  }



#ifdef CONFIG_H8300

/* h8300 don't have SCIF */

#define CPU_SCIF_FNS(name)						\

  static inline unsigned int sci_##name##_in(struct uart_port *port)	\

  {									\

    return 0;								\

  }									\

  static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \

  {									\

  }

#else

#define CPU_SCIF_FNS(name, scif_offset, scif_size)			\

  static inline unsigned int sci_##name##_in(struct uart_port *port)	\

  {									\
@@ -243,7 +221,6 @@ 
  {									\

    SCI_OUT(scif_size, scif_offset, value);				\

  }

#endif



#define CPU_SCI_FNS(name, sci_offset, sci_size)				\

  static inline unsigned int sci_##name##_in(struct uart_port* port)	\
@@ -262,8 +239,7 @@ 
    defined(CONFIG_ARCH_SH7372)

#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)

#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \

		                sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \

		                 h8_sci_offset, h8_sci_size) \

		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

  CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)

#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

	  CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
@@ -282,19 +258,11 @@ 
  CPU_SCIF_FNS(name, scif_offset, scif_size)

#else

#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \

		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \

                 h8_sci_offset, h8_sci_size) \

		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

  CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)

#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

  CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)

#endif

#elif defined(__H8300H__) || defined(__H8300S__)

#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \

		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \

                 h8_sci_offset, h8_sci_size) \

  CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)

#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

  CPU_SCIF_FNS(name)

#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\

      defined(CONFIG_CPU_SUBTYPE_SH7724)

        #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
@@ -303,8 +271,7 @@ 
                CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)

#else

#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \

		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \

		 h8_sci_offset, h8_sci_size) \

		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

  CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)

#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \

  CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
@@ -353,14 +320,14 @@ SCIF_FNS(SCFCR, 0x18, 16) 
SCIF_FNS(SCFDR,  0x1c, 16)

SCIF_FNS(SCLSR,  0x24, 16)

#else

/*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/

/*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/

SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)

SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)

SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)

SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)

SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)

SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)

/*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  */

/*      name     off  sz   off  sz   off  sz   off  sz   */

SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16)

SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8)

SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16)

SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8)

SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16)

SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8)

SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)

#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \

    defined(CONFIG_CPU_SUBTYPE_SH7780) || \
@@ -390,48 +357,6 @@ SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 
#define sci_in(port, reg) sci_##reg##_in(port)

#define sci_out(port, reg, value) sci_##reg##_out(port, value)



/* H8/300 series SCI pins assignment */

#if defined(__H8300H__) || defined(__H8300S__)

static const struct __attribute__((packed)) {

	int port;             /* GPIO port no */

	unsigned short rx,tx; /* GPIO bit no */

} h8300_sci_pins[] = {

#if defined(CONFIG_H83007) || defined(CONFIG_H83068)

	{    /* SCI0 */

		.port = H8300_GPIO_P9,

		.rx   = H8300_GPIO_B2,

		.tx   = H8300_GPIO_B0,

	},

	{    /* SCI1 */

		.port = H8300_GPIO_P9,

		.rx   = H8300_GPIO_B3,

		.tx   = H8300_GPIO_B1,

	},

	{    /* SCI2 */

		.port = H8300_GPIO_PB,

		.rx   = H8300_GPIO_B7,

		.tx   = H8300_GPIO_B6,

	}

#elif defined(CONFIG_H8S2678)

	{    /* SCI0 */

		.port = H8300_GPIO_P3,

		.rx   = H8300_GPIO_B2,

		.tx   = H8300_GPIO_B0,

	},

	{    /* SCI1 */

		.port = H8300_GPIO_P3,

		.rx   = H8300_GPIO_B3,

		.tx   = H8300_GPIO_B1,

	},

	{    /* SCI2 */

		.port = H8300_GPIO_P5,

		.rx   = H8300_GPIO_B1,

		.tx   = H8300_GPIO_B0,

	}

#endif

};

#endif



#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \

    defined(CONFIG_CPU_SUBTYPE_SH7707) || \

    defined(CONFIG_CPU_SUBTYPE_SH7708) || \
@@ -454,12 +379,6 @@ static inline int sci_rxd_in(struct uart_port *port) 
		return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */

	return 1;

}

#elif defined(__H8300H__) || defined(__H8300S__)

static inline int sci_rxd_in(struct uart_port *port)

{

	int ch = (port->mapbase - SMR0) >> 3;

	return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;

}

#else /* default case for non-SCI processors */

static inline int sci_rxd_in(struct uart_port *port)

{