Loading Documentation/admin-guide/kernel-parameters.txt +3 −0 Original line number Diff line number Diff line Loading @@ -1974,6 +1974,9 @@ off Disables hypervisor mitigations and doesn't emit any warnings. It also drops the swap size and available RAM limit restriction on both hypervisor and bare metal. Default is 'flush'. Loading Documentation/admin-guide/l1tf.rst +5 −1 Original line number Diff line number Diff line Loading @@ -405,6 +405,9 @@ time with the option "l1tf=". The valid arguments for this option are: off Disables hypervisor mitigations and doesn't emit any warnings. It also drops the swap size and available RAM limit restrictions on both hypervisor and bare metal. ============ ============================================================= The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`. Loading Loading @@ -576,7 +579,8 @@ Default mitigations The kernel default mitigations for vulnerable processors are: - PTE inversion to protect against malicious user space. This is done unconditionally and cannot be controlled. unconditionally and cannot be controlled. The swap storage is limited to ~16TB. - L1D conditional flushing on VMENTER when EPT is enabled for a guest. Loading Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 90 SUBLEVEL = 92 EXTRAVERSION = NAME = Petit Gorille Loading arch/arm64/include/asm/kvm_arm.h +1 −1 Original line number Diff line number Diff line Loading @@ -99,7 +99,7 @@ TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) /* VTCR_EL2 Registers bits */ #define VTCR_EL2_RES1 (1 << 31) #define VTCR_EL2_RES1 (1U << 31) #define VTCR_EL2_HD (1 << 22) #define VTCR_EL2_HA (1 << 21) #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK Loading arch/mips/boot/compressed/calc_vmlinuz_load_addr.c +4 −3 Original line number Diff line number Diff line Loading @@ -13,6 +13,7 @@ #include <stdint.h> #include <stdio.h> #include <stdlib.h> #include "../../../../include/linux/sizes.h" int main(int argc, char *argv[]) { Loading Loading @@ -45,11 +46,11 @@ int main(int argc, char *argv[]) vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size; /* * Align with 16 bytes: "greater than that used for any standard data * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition). * Align with 64KB: KEXEC needs load sections to be aligned to PAGE_SIZE, * which may be as large as 64KB depending on the kernel configuration. */ vmlinuz_load_addr += (16 - vmlinux_size % 16); vmlinuz_load_addr += (SZ_64K - vmlinux_size % SZ_64K); printf("0x%llx\n", vmlinuz_load_addr); Loading Loading
Documentation/admin-guide/kernel-parameters.txt +3 −0 Original line number Diff line number Diff line Loading @@ -1974,6 +1974,9 @@ off Disables hypervisor mitigations and doesn't emit any warnings. It also drops the swap size and available RAM limit restriction on both hypervisor and bare metal. Default is 'flush'. Loading
Documentation/admin-guide/l1tf.rst +5 −1 Original line number Diff line number Diff line Loading @@ -405,6 +405,9 @@ time with the option "l1tf=". The valid arguments for this option are: off Disables hypervisor mitigations and doesn't emit any warnings. It also drops the swap size and available RAM limit restrictions on both hypervisor and bare metal. ============ ============================================================= The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`. Loading Loading @@ -576,7 +579,8 @@ Default mitigations The kernel default mitigations for vulnerable processors are: - PTE inversion to protect against malicious user space. This is done unconditionally and cannot be controlled. unconditionally and cannot be controlled. The swap storage is limited to ~16TB. - L1D conditional flushing on VMENTER when EPT is enabled for a guest. Loading
Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 90 SUBLEVEL = 92 EXTRAVERSION = NAME = Petit Gorille Loading
arch/arm64/include/asm/kvm_arm.h +1 −1 Original line number Diff line number Diff line Loading @@ -99,7 +99,7 @@ TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) /* VTCR_EL2 Registers bits */ #define VTCR_EL2_RES1 (1 << 31) #define VTCR_EL2_RES1 (1U << 31) #define VTCR_EL2_HD (1 << 22) #define VTCR_EL2_HA (1 << 21) #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK Loading
arch/mips/boot/compressed/calc_vmlinuz_load_addr.c +4 −3 Original line number Diff line number Diff line Loading @@ -13,6 +13,7 @@ #include <stdint.h> #include <stdio.h> #include <stdlib.h> #include "../../../../include/linux/sizes.h" int main(int argc, char *argv[]) { Loading Loading @@ -45,11 +46,11 @@ int main(int argc, char *argv[]) vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size; /* * Align with 16 bytes: "greater than that used for any standard data * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition). * Align with 64KB: KEXEC needs load sections to be aligned to PAGE_SIZE, * which may be as large as 64KB depending on the kernel configuration. */ vmlinuz_load_addr += (16 - vmlinux_size % 16); vmlinuz_load_addr += (SZ_64K - vmlinux_size % SZ_64K); printf("0x%llx\n", vmlinuz_load_addr); Loading