Merge "ARM: dts: msm: Add QUPV3 SE dt node for spi on trinket" (aa70e443) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi

+200 −0

Original line number	Diff line number	Diff line
		@@ -408,5 +408,205 @@
		};
		};
		};

		/* SPI Instances */
		/* SE 0 pin mappings */
		qupv3_se0_spi_pins: qupv3_se0_spi_pins {
		qupv3_se0_spi_active: qupv3_se0_spi_active {
		mux {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		function = "qup00";
		};

		config {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
		mux {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		function = "gpio";
		};

		configs {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 2 pin mappings */
		qupv3_se2_spi_pins: qupv3_se2_spi_pins {
		qupv3_se2_spi_active: qupv3_se2_spi_active {
		mux {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		function = "qup02";
		};

		config {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
		mux {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		function = "gpio";
		};

		configs {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 5 pin mappings */
		qupv3_se5_spi_pins: qupv3_se5_spi_pins {
		qupv3_se5_spi_active: qupv3_se5_spi_active {
		mux {
		pins = "gpio22", "gpio23", "gpio24",
		"gpio25";
		function = "qup10";
		};

		config {
		pins = "gpio22", "gpio23", "gpio24",
		"gpio25";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
		mux {
		pins = "gpio22", "gpio23", "gpio24",
		"gpio25";
		function = "gpio";
		};

		configs {
		pins = "gpio22", "gpio23", "gpio24",
		"gpio25";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 6 pin mappings */
		qupv3_se6_spi_pins: qupv3_se6_spi_pins {
		qupv3_se6_spi_active: qupv3_se6_spi_active {
		mux {
		pins = "gpio30", "gpio31", "gpio32",
		"gpio33";
		function = "qup11";
		};

		config {
		pins = "gpio30", "gpio31", "gpio32",
		"gpio33";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
		mux {
		pins = "gpio30", "gpio31", "gpio32",
		"gpio33";
		function = "gpio";
		};

		configs {
		pins = "gpio30", "gpio31", "gpio32",
		"gpio33";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 8 pin mappings */
		qupv3_se8_spi_pins: qupv3_se8_spi_pins {
		qupv3_se8_spi_active: qupv3_se8_spi_active {
		mux {
		pins = "gpio18", "gpio19", "gpio20",
		"gpio21";
		function = "qup13";
		};

		config {
		pins = "gpio18", "gpio19", "gpio20",
		"gpio21";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
		mux {
		pins = "gpio18", "gpio19", "gpio20",
		"gpio21";
		function = "gpio";
		};

		configs {
		pins = "gpio18", "gpio19", "gpio20",
		"gpio21";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 9 pin mappings */
		qupv3_se9_spi_pins: qupv3_se9_spi_pins {
		qupv3_se9_spi_active: qupv3_se9_spi_active {
		mux {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		function = "qup_14";
		};

		config {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
		mux {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		function = "gpio";
		};

		configs {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		};
		};

arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi

+145 −10

Original line number	Diff line number	Diff line
		@@ -178,6 +178,51 @@
		status = "disabled";
		};

		/* SPI Instances */
		qupv3_se0_spi: spi@4a80000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x04a80000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_spi_active>;
		pinctrl-1 = <&qupv3_se0_spi_sleep>;
		interrupts = <GIC_SPI 327 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		dmas = <&gpi_dma0 0 0 1 64 0>,
		<&gpi_dma0 1 0 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se2_spi: spi@4a88000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x04a88000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_spi_active>;
		pinctrl-1 = <&qupv3_se2_spi_sleep>;
		interrupts = <GIC_SPI 329 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		dmas = <&gpi_dma0 0 2 1 64 0>,
		<&gpi_dma0 1 2 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		/* QUPv3_1 instances */
		qupv3_1: qcom,qupv3_1_geni_se@4cc0000 {
		compatible = "qcom,qupv3-geni-se";
		@@ -227,8 +272,8 @@
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 0 3 64 0>,
		<&gpi_dma0 1 0 3 64 0>;
		dmas = <&gpi_dma1 0 0 3 64 0>,
		<&gpi_dma1 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_i2c_active>;
		@@ -247,8 +292,8 @@
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 1 3 64 0>,
		<&gpi_dma0 1 1 3 64 0>;
		dmas = <&gpi_dma1 0 1 3 64 0>,
		<&gpi_dma1 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		@@ -267,8 +312,8 @@
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
		<&gpi_dma0 1 2 3 64 0>;
		dmas = <&gpi_dma1 0 2 3 64 0>,
		<&gpi_dma1 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_i2c_active>;
		@@ -287,8 +332,8 @@
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 3 3 64 0>,
		<&gpi_dma0 1 3 3 64 0>;
		dmas = <&gpi_dma1 0 3 3 64 0>,
		<&gpi_dma1 1 3 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		@@ -307,8 +352,8 @@
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 4 3 64 0>,
		<&gpi_dma0 1 4 3 64 0>;
		dmas = <&gpi_dma1 0 4 3 64 0>,
		<&gpi_dma1 1 4 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_i2c_active>;
		@@ -316,4 +361,94 @@
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		/* SPI Instances */
		qupv3_se5_spi: spi@4c80000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x04c80000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_spi_active>;
		pinctrl-1 = <&qupv3_se5_spi_sleep>;
		interrupts = <GIC_SPI 308 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 0 1 64 0>,
		<&gpi_dma1 1 0 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se6_spi: spi@4c84000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x04c84000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_spi_active>;
		pinctrl-1 = <&qupv3_se6_spi_sleep>;
		interrupts = <GIC_SPI 309 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 1 1 64 0>,
		<&gpi_dma1 1 1 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se8_spi: spi@4c8c000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x04c8c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_spi_active>;
		pinctrl-1 = <&qupv3_se8_spi_sleep>;
		interrupts = <GIC_SPI 311 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 3 1 64 0>,
		<&gpi_dma1 1 3 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se9_spi: spi@4c90000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x04c90000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_spi_active>;
		pinctrl-1 = <&qupv3_se9_spi_sleep>;
		interrupts = <GIC_SPI 312 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 4 1 64 0>,
		<&gpi_dma1 1 4 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		};