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Commit aa1cf632 authored by David Gibson's avatar David Gibson Committed by Paul Mackerras
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[POWERPC] Fix small race in 44x tlbie function 



The 440 family of processors don't have a tlbie instruction.  So, we
implement TLB invalidates by explicitly searching the TLB with tlbsx.,
then clobbering the relevant entry, if any.  Unfortunately the PID for
the search needs to be stored in the MMUCR register, which is also
used by the TLB miss handler.  Interrupts were enabled in _tlbie(), so
an interrupt between loading the MMUCR and the tlbsx could cause
incorrect search results, and thus a failure to invalide TLB entries
which needed to be invalidated.

This fixes the problem in both arch/ppc and arch/powerpc by inhibiting
interrupts (even critical and debug interrupts) across the relevant
instructions.

Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Acked-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent fa6b769a

arch/powerpc/kernel/misc_32.S

+11 −1
Original line number Original line Diff line number Diff line
@@ -301,9 +301,19 @@ _GLOBAL(_tlbie) 
	mfspr	r4,SPRN_MMUCR

	mfspr	r4,SPRN_MMUCR

	mfspr	r5,SPRN_PID			/* Get PID */

	mfspr	r5,SPRN_PID			/* Get PID */

	rlwimi	r4,r5,0,24,31			/* Set TID */

	rlwimi	r4,r5,0,24,31			/* Set TID */

	mtspr	SPRN_MMUCR,r4





	/* We have to run the search with interrupts disabled, even critical

	 * and debug interrupts (in fact the only critical exceptions we have

	 * are debug and machine check).  Otherwise  an interrupt which causes

	 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */

	mfmsr	r5

	lis	r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha

	addi	r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l

	andc	r6,r5,r6

	mtmsr	r6

	mtspr	SPRN_MMUCR,r4

	tlbsx.	r3, 0, r3

	tlbsx.	r3, 0, r3

	mtmsr	r5

	bne	10f

	bne	10f

	sync

	sync

	/* There are only 64 TLB entries, so r3 < 64,

	/* There are only 64 TLB entries, so r3 < 64,

arch/ppc/kernel/misc.S

+11 −1
Original line number Original line Diff line number Diff line
@@ -237,9 +237,19 @@ _GLOBAL(_tlbie) 
	mfspr	r4,SPRN_MMUCR

	mfspr	r4,SPRN_MMUCR

	mfspr	r5,SPRN_PID			/* Get PID */

	mfspr	r5,SPRN_PID			/* Get PID */

	rlwimi	r4,r5,0,24,31			/* Set TID */

	rlwimi	r4,r5,0,24,31			/* Set TID */

	mtspr	SPRN_MMUCR,r4





	/* We have to run the search with interrupts disabled, even critical

	 * and debug interrupts (in fact the only critical exceptions we have

	 * are debug and machine check).  Otherwise  an interrupt which causes

	 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */

	mfmsr	r5

	lis	r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha

	addi	r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l

	andc	r6,r5,r6

	mtmsr	r6

	mtspr	SPRN_MMUCR,r4

	tlbsx.	r3, 0, r3

	tlbsx.	r3, 0, r3

	mtmsr	r5

	bne	10f

	bne	10f

	sync

	sync

	/* There are only 64 TLB entries, so r3 < 64,

	/* There are only 64 TLB entries, so r3 < 64,