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Commit aa178fec authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I10330536,I1993f031 into dev/msm-4.14-display 

* changes:
  ARM: dts: msm: enable display rsc for sm8150
  drm/msm: vote for mdss core in disp rsc during probe
parents 4765dd0d 1dbd9790

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -395,7 +395,7 @@ 
};



&mdss_mdp {

	connectors = <&sde_wb &sde_dp &sde_dsi>;

	connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>;

};



/* PHY TIMINGS REVISION P */

arch/arm64/boot/dts/qcom/sm8150-sde-pll.dtsi

+0 −17
Original line number Diff line number Diff line
@@ -79,8 +79,6 @@ 
		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";



		gdsc-supply = <&mdss_core_gdsc>;



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,
@@ -89,21 +87,6 @@ 
		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk", "pipe_clk";

		clock-rate = <0>;



		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};



		};

	};



};

arch/arm64/boot/dts/qcom/sm8150-sde.dtsi

+10 −21
Original line number Diff line number Diff line
@@ -24,15 +24,19 @@ 
		clocks =

			<&clock_gcc GCC_DISP_AHB_CLK>,

			<&clock_gcc GCC_DISP_HF_AXI_CLK>,

			<&clock_gcc GCC_DISP_SF_AXI_CLK>,

			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,

			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;

		clock-names = "gcc_iface", "gcc_bus",

				"iface_clk", "core_clk", "vsync_clk";

		clock-rate = <0 0 0 300000000 19200000>;

		clock-max-rate = <0 0 0 460000000 19200000>;

			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,

			<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;

		clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",

				"iface_clk", "core_clk", "vsync_clk",

				"rot_clk";

		clock-rate = <0 0 0 0 300000000 19200000 0>;

		clock-max-rate = <0 0 0 0 460000000 19200000 0>;



		sde-vdd-supply = <&mdss_core_gdsc>;

		mmcx-supply = <&VDD_MMCX_LEVEL>;



		/* interrupt config */

		interrupts = <0 83 0>;
@@ -248,7 +252,7 @@ 


			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "sde-vdd";

				qcom,supply-name = "mmcx";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;
@@ -311,7 +315,6 @@ 
			<0xaf30000 0x3fd4>;

		reg-names = "drv", "wrapper";

		qcom,sde-rsc-version = <2>;

		status = "disabled";



		vdd-supply = <&mdss_core_gdsc>;

		clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
@@ -358,20 +361,6 @@ 
			    <20000 20512 0 6400000>,

			    <20000 20512 0 6400000>;

		};



		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "mmcx";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_rotator: qcom,mdss_rotator@ae00000 {

drivers/gpu/drm/msm/sde_rsc.c

+10 −0
Original line number Diff line number Diff line
@@ -1246,6 +1246,8 @@ static void sde_rsc_deinit(struct platform_device *pdev, 


	if (rsc->pclient)

		sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, false);

	if (rsc->sw_fs_enabled)

		regulator_disable(rsc->fs);

	if (rsc->fs)

		devm_regulator_put(rsc->fs);

	if (rsc->wrapper_io.base)
@@ -1405,6 +1407,14 @@ static int sde_rsc_probe(struct platform_device *pdev) 
		goto sde_rsc_fail;

	}



	ret = regulator_enable(rsc->fs);

	if (ret) {

		pr_err("sde rsc: fs on failed ret:%d\n", ret);

		goto sde_rsc_fail;

	}



	rsc->sw_fs_enabled = true;



	if (sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, true)) {

		pr_err("failed to enable sde rsc power resources\n");

		goto sde_rsc_fail;

drivers/gpu/drm/msm/sde_rsc_hw.c

+11 −4
Original line number Diff line number Diff line
@@ -609,11 +609,13 @@ static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc) 
	if (rsc->power_collapse_block)

		return -EINVAL;



	if (rsc->sw_fs_enabled) {

		rc = regulator_set_mode(rsc->fs, REGULATOR_MODE_FAST);

		if (rc) {

			pr_err("vdd reg fast mode set failed rc:%d\n", rc);

			return rc;

		}

	}



	dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,

						0x7, rsc->debug_mode);
@@ -647,6 +649,11 @@ static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc) 


	rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_PC);



	if (rsc->sw_fs_enabled) {

		regulator_disable(rsc->fs);

		rsc->sw_fs_enabled = false;

	}



	return 0;



end: