net/mlx5: FPGA, Add SBU infrastructure (a9956d35) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/net/ethernet/mellanox/mlx5/core/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -6,7 +6,7 @@ mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
		mad.o transobj.o vport.o sriov.o fs_cmd.o fs_core.o \
		fs_counters.o rl.o lag.o dev.o lib/gid.o

		mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o
		mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o

		mlx5_core-$(CONFIG_MLX5_CORE_EN) += wq.o eswitch.o eswitch_offloads.o \
		en_main.o en_common.o en_fs.o en_ethtool.o en_tx.o \

drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c

+65 −0

Original line number	Diff line number	Diff line
		@@ -38,6 +38,39 @@
		#include "mlx5_core.h"
		#include "fpga/cmd.h"

		#define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
		MLX5_FPGA_ACCESS_REG_SIZE_MAX)

		int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
		void *buf, bool write)
		{
		u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
		u32 out[MLX5_FPGA_ACCESS_REG_SZ];
		int err;

		if (size & 3)
		return -EINVAL;
		if (addr & 3)
		return -EINVAL;
		if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
		return -EINVAL;

		MLX5_SET(fpga_access_reg, in, size, size);
		MLX5_SET64(fpga_access_reg, in, address, addr);
		if (write)
		memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);

		err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
		MLX5_REG_FPGA_ACCESS_REG, 0, write);
		if (err)
		return err;

		if (!write)
		memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);

		return 0;
		}

		int mlx5_fpga_caps(struct mlx5_core_dev dev, u32 caps)
		{
		u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
		@@ -58,6 +91,38 @@ int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
		MLX5_REG_FPGA_CTRL, 0, true);
		}

		int mlx5_fpga_sbu_caps(struct mlx5_core_dev dev, void caps, int size)
		{
		unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
		u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
		unsigned int read;
		int ret = 0;

		if (cap_size > size) {
		mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
		size, cap_size);
		return -EINVAL;
		}

		while (cap_size > 0) {
		read = min_t(unsigned int, cap_size,
		MLX5_FPGA_ACCESS_REG_SIZE_MAX);

		ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
		if (ret) {
		mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address 0x%llx: %d",
		read, addr, ret);
		return ret;
		}

		cap_size -= read;
		addr += read;
		caps += read;
		}

		return ret;
		}

		int mlx5_fpga_query(struct mlx5_core_dev dev, struct mlx5_fpga_query query)
		{
		u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};

drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -68,6 +68,9 @@ struct mlx5_fpga_qp_counters {
		int mlx5_fpga_caps(struct mlx5_core_dev dev, u32 caps);
		int mlx5_fpga_query(struct mlx5_core_dev dev, struct mlx5_fpga_query query);
		int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
		int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
		void *buf, bool write);
		int mlx5_fpga_sbu_caps(struct mlx5_core_dev dev, void caps, int size);

		int mlx5_fpga_create_qp(struct mlx5_core_dev dev, void fpga_qpc,
		u32 *fpga_qpn);

drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.c

0 → 100644

+164 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2017 Mellanox Technologies. All rights reserved.
		*
		* This software is available to you under a choice of one of two
		* licenses. You may choose to be licensed under the terms of the GNU
		* General Public License (GPL) Version 2, available from the file
		* COPYING in the main directory of this source tree, or the
		* OpenIB.org BSD license below:
		*
		* Redistribution and use in source and binary forms, with or
		* without modification, are permitted provided that the following
		* conditions are met:
		*
		* - Redistributions of source code must retain the above
		* copyright notice, this list of conditions and the following
		* disclaimer.
		*
		* - Redistributions in binary form must reproduce the above
		* copyright notice, this list of conditions and the following
		* disclaimer in the documentation and/or other materials
		* provided with the distribution.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
		* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
		* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
		* SOFTWARE.
		*
		*/

		#include <linux/mlx5/device.h>

		#include "fpga/core.h"
		#include "fpga/conn.h"
		#include "fpga/sdk.h"

		struct mlx5_fpga_conn *
		mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
		struct mlx5_fpga_conn_attr *attr)
		{
		return mlx5_fpga_conn_create(fdev, attr, MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP);
		}
		EXPORT_SYMBOL(mlx5_fpga_sbu_conn_create);

		void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn)
		{
		mlx5_fpga_conn_destroy(conn);
		}
		EXPORT_SYMBOL(mlx5_fpga_sbu_conn_destroy);

		int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
		struct mlx5_fpga_dma_buf *buf)
		{
		return mlx5_fpga_conn_send(conn, buf);
		}
		EXPORT_SYMBOL(mlx5_fpga_sbu_conn_sendmsg);

		static int mlx5_fpga_mem_read_i2c(struct mlx5_fpga_device *fdev, size_t size,
		u64 addr, u8 *buf)
		{
		size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
		size_t bytes_done = 0;
		u8 actual_size;
		int err;

		if (!fdev->mdev)
		return -ENOTCONN;

		while (bytes_done < size) {
		actual_size = min(max_size, (size - bytes_done));

		err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
		addr + bytes_done,
		buf + bytes_done, false);
		if (err) {
		mlx5_fpga_err(fdev, "Failed to read over I2C: %d\n",
		err);
		break;
		}

		bytes_done += actual_size;
		}

		return err;
		}

		static int mlx5_fpga_mem_write_i2c(struct mlx5_fpga_device *fdev, size_t size,
		u64 addr, u8 *buf)
		{
		size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
		size_t bytes_done = 0;
		u8 actual_size;
		int err;

		if (!fdev->mdev)
		return -ENOTCONN;

		while (bytes_done < size) {
		actual_size = min(max_size, (size - bytes_done));

		err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
		addr + bytes_done,
		buf + bytes_done, true);
		if (err) {
		mlx5_fpga_err(fdev, "Failed to write FPGA crspace\n");
		break;
		}

		bytes_done += actual_size;
		}

		return err;
		}

		int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
		void *buf, enum mlx5_fpga_access_type access_type)
		{
		int ret;

		switch (access_type) {
		case MLX5_FPGA_ACCESS_TYPE_I2C:
		ret = mlx5_fpga_mem_read_i2c(fdev, size, addr, buf);
		if (ret)
		return ret;
		break;
		default:
		mlx5_fpga_warn(fdev, "Unexpected read access_type %u\n",
		access_type);
		return -EACCES;
		}

		return size;
		}
		EXPORT_SYMBOL(mlx5_fpga_mem_read);

		int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
		void *buf, enum mlx5_fpga_access_type access_type)
		{
		int ret;

		switch (access_type) {
		case MLX5_FPGA_ACCESS_TYPE_I2C:
		ret = mlx5_fpga_mem_write_i2c(fdev, size, addr, buf);
		if (ret)
		return ret;
		break;
		default:
		mlx5_fpga_warn(fdev, "Unexpected write access_type %u\n",
		access_type);
		return -EACCES;
		}

		return size;
		}
		EXPORT_SYMBOL(mlx5_fpga_mem_write);

		int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device fdev, int size, void buf)
		{
		return mlx5_fpga_sbu_caps(fdev->mdev, buf, size);
		}
		EXPORT_SYMBOL(mlx5_fpga_get_sbu_caps);

drivers/net/ethernet/mellanox/mlx5/core/fpga/sdk.h

+98 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,11 @@
		* This header defines the in-kernel API for Innova FPGA client drivers.
		*/

		enum mlx5_fpga_access_type {
		MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
		MLX5_FPGA_ACCESS_TYPE_DONTCARE = 0x0,
		};

		struct mlx5_fpga_conn;
		struct mlx5_fpga_device;

		@@ -103,4 +108,97 @@ struct mlx5_fpga_conn_attr {
		void *cb_arg;
		};

		/**
		* mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection
		* @fdev: The FPGA device
		* @attr: Attributes of the new connection
		*
		* Sets up a new FPGA SBU connection with the specified attributes.
		* The receive callback function may be called for incoming messages even
		* before this function returns.
		*
		* The caller must eventually destroy the connection by calling
		* mlx5_fpga_sbu_conn_destroy.
		*
		* Return: A new connection, or ERR_PTR() error value otherwise.
		*/
		struct mlx5_fpga_conn *
		mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
		struct mlx5_fpga_conn_attr *attr);

		/**
		* mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection
		* @conn: The FPGA SBU connection to destroy
		*
		* Cleans up an FPGA SBU connection which was previously created with
		* mlx5_fpga_sbu_conn_create.
		*/
		void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn);

		/**
		* mlx5_fpga_sbu_conn_sendmsg() - Queue the transmission of a packet
		* @fdev: An FPGA SBU connection
		* @buf: The packet buffer
		*
		* Queues a packet for transmission over an FPGA SBU connection.
		* The buffer should not be modified or freed until completion.
		* Upon completion, the buf's complete() callback is invoked, indicating the
		* success or error status of the transmission.
		*
		* Return: 0 if successful, or an error value otherwise.
		*/
		int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
		struct mlx5_fpga_dma_buf *buf);

		/**
		* mlx5_fpga_mem_read() - Read from FPGA memory address space
		* @fdev: The FPGA device
		* @size: Size of chunk to read, in bytes
		* @addr: Starting address to read from, in FPGA address space
		* @buf: Buffer to read into
		* @access_type: Method for reading
		*
		* Reads from the specified address into the specified buffer.
		* The address may point to configuration space or to DDR.
		* Large reads may be performed internally as several non-atomic operations.
		* This function may sleep, so should not be called from atomic contexts.
		*
		* Return: 0 if successful, or an error value otherwise.
		*/
		int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
		void *buf, enum mlx5_fpga_access_type access_type);

		/**
		* mlx5_fpga_mem_write() - Write to FPGA memory address space
		* @fdev: The FPGA device
		* @size: Size of chunk to write, in bytes
		* @addr: Starting address to write to, in FPGA address space
		* @buf: Buffer which contains data to write
		* @access_type: Method for writing
		*
		* Writes the specified buffer data to FPGA memory at the specified address.
		* The address may point to configuration space or to DDR.
		* Large writes may be performed internally as several non-atomic operations.
		* This function may sleep, so should not be called from atomic contexts.
		*
		* Return: 0 if successful, or an error value otherwise.
		*/
		int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
		void *buf, enum mlx5_fpga_access_type access_type);

		/**
		* mlx5_fpga_get_sbu_caps() - Read the SBU capabilities
		* @fdev: The FPGA device
		* @size: Size of the buffer to read into
		* @buf: Buffer to read the capabilities into
		*
		* Reads the FPGA SBU capabilities into the specified buffer.
		* The format of the capabilities buffer is SBU-dependent.
		*
		* Return: 0 if successful
		* -EINVAL if the buffer is not large enough to contain SBU caps
		* or any other error value otherwise.
		*/
		int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device fdev, int size, void buf);

		#endif /* MLX5_FPGA_SDK_H */