Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a977dbe8 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Reduce 57765 core clock when link at 10Mbps 



This patch reduces the core clock to 6.25MHz when operating at 10Mbps
link speed.  This is needed to prevent a bug that will ultimately cause
transmits to cease.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1a319025

drivers/net/tg3.c

+5 −0
Original line number Diff line number Diff line
@@ -7654,6 +7654,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);



		tw32(GRC_MODE, grc_mode);



		val = tr32(TG3_CPMU_LSPD_10MB_CLK);

		val &= ~CPMU_LSPD_10MB_MACCLK_MASK;

		val |= CPMU_LSPD_10MB_MACCLK_6_25;

		tw32(TG3_CPMU_LSPD_10MB_CLK, val);

	}



	/* This works around an issue with Athlon chipsets on