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Commit a949307d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes Id28f8025,Idccaa794,I4c92f3cf into dev/msm-4.14-display 

* changes:
  drm/msm/sde: Fix 32-bit compilation issues
  drm/msm/sde: prevent clearing multirect flags during validate failure
  drm/msm/sde: Increase command mode idle timeout in early wake-up
parents 06e40f51 0a3bfd67

drivers/gpu/drm/msm/dp/dp_debug.c

+2 −2
Original line number Diff line number Diff line
@@ -801,7 +801,7 @@ static ssize_t dp_debug_write_hdr(struct file *file, 
	struct sde_connector *c_conn;

	struct sde_connector_state *c_state;

	struct dp_debug_private *debug = file->private_data;

	char buf[SZ_1K];

	char buf[SZ_512];

	size_t len = 0;



	if (!debug)
@@ -815,7 +815,7 @@ static ssize_t dp_debug_write_hdr(struct file *file, 
	c_state = to_sde_connector_state(connector->state);



	/* Leave room for termination char */

	len = min_t(size_t, count, SZ_1K - 1);

	len = min_t(size_t, count, SZ_512 - 1);

	if (copy_from_user(buf, user_buff, len))

		goto end;

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h

+4 −8
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ enum dsi_status_int_type { 
 * @DSI_EINT_DLN0_ESC_ENTRY_ERR:         Incorrect LP Rx escape entry.

 * @DSI_EINT_DLN0_ESC_SYNC_ERR:          LP Rx data is not byte aligned.

 * @DSI_EINT_DLN0_LP_CONTROL_ERR:        Incorrect LP Rx state sequence.

 * @DSI_EINT_PENDING_HS_TX_TIMEOUT:      Pending High-speed transfer timeout.

 * @DSI_EINT_PANEL_SPECIFIC_ERR:         DSI Protocol violation error.

 * @DSI_EINT_INTERLEAVE_OP_CONTENTION:   Interleave operation contention.

 * @DSI_EINT_CMD_DMA_FIFO_UNDERFLOW:     Command mode DMA FIFO underflow.

 * @DSI_EINT_CMD_MDP_FIFO_UNDERFLOW:     Command MDP FIFO underflow (failed to
@@ -182,7 +182,6 @@ enum dsi_status_int_type { 
 * @DSI_EINT_DLN1_LP1_CONTENTION:        PHY level contention while lane 1 high.

 * @DSI_EINT_DLN2_LP1_CONTENTION:        PHY level contention while lane 2 high.

 * @DSI_EINT_DLN3_LP1_CONTENTION:        PHY level contention while lane 3 high.

 * @DSI_EINT_PANEL_SPECIFIC_ERR:         DSI Protocol violation error.

 */

enum dsi_error_int_index {

	DSI_EINT_RDBK_SINGLE_ECC_ERR = 0,
@@ -197,7 +196,7 @@ enum dsi_error_int_index { 
	DSI_EINT_DLN0_ESC_ENTRY_ERR = 9,

	DSI_EINT_DLN0_ESC_SYNC_ERR = 10,

	DSI_EINT_DLN0_LP_CONTROL_ERR = 11,

	DSI_EINT_PENDING_HS_TX_TIMEOUT = 12,

	DSI_EINT_PANEL_SPECIFIC_ERR = 12,

	DSI_EINT_INTERLEAVE_OP_CONTENTION = 13,

	DSI_EINT_CMD_DMA_FIFO_UNDERFLOW = 14,

	DSI_EINT_CMD_MDP_FIFO_UNDERFLOW = 15,
@@ -217,7 +216,6 @@ enum dsi_error_int_index { 
	DSI_EINT_DLN1_LP1_CONTENTION = 29,

	DSI_EINT_DLN2_LP1_CONTENTION = 30,

	DSI_EINT_DLN3_LP1_CONTENTION = 31,

	DSI_EINT_PANEL_SPECIFIC_ERR = 32,



	DSI_ERROR_INTERRUPT_COUNT

};
@@ -236,7 +234,7 @@ enum dsi_error_int_index { 
 * @DSI_DLN0_ESC_ENTRY_ERR:         Incorrect LP Rx escape entry.

 * @DSI_DLN0_ESC_SYNC_ERR:          LP Rx data is not byte aligned.

 * @DSI_DLN0_LP_CONTROL_ERR:        Incorrect LP Rx state sequence.

 * @DSI_PENDING_HS_TX_TIMEOUT:      Pending High-speed transfer timeout.

 * @DSI_PANEL_SPECIFIC_ERR:         DSI Protocol violation.

 * @DSI_INTERLEAVE_OP_CONTENTION:   Interleave operation contention.

 * @DSI_CMD_DMA_FIFO_UNDERFLOW:     Command mode DMA FIFO underflow.

 * @DSI_CMD_MDP_FIFO_UNDERFLOW:     Command MDP FIFO underflow (failed to
@@ -257,7 +255,6 @@ enum dsi_error_int_index { 
 * @DSI_DLN1_LP1_CONTENTION:        PHY level contention while lane 1 is high.

 * @DSI_DLN2_LP1_CONTENTION:        PHY level contention while lane 2 is high.

 * @DSI_DLN3_LP1_CONTENTION:        PHY level contention while lane 3 is high.

 * @DSI_PANEL_SPECIFIC_ERR:         DSI Protocol violation.

 */

enum dsi_error_int_type {

	DSI_RDBK_SINGLE_ECC_ERR = BIT(DSI_EINT_RDBK_SINGLE_ECC_ERR),
@@ -272,7 +269,7 @@ enum dsi_error_int_type { 
	DSI_DLN0_ESC_ENTRY_ERR = BIT(DSI_EINT_DLN0_ESC_ENTRY_ERR),

	DSI_DLN0_ESC_SYNC_ERR = BIT(DSI_EINT_DLN0_ESC_SYNC_ERR),

	DSI_DLN0_LP_CONTROL_ERR = BIT(DSI_EINT_DLN0_LP_CONTROL_ERR),

	DSI_PENDING_HS_TX_TIMEOUT = BIT(DSI_EINT_PENDING_HS_TX_TIMEOUT),

	DSI_PANEL_SPECIFIC_ERR = BIT(DSI_EINT_PANEL_SPECIFIC_ERR),

	DSI_INTERLEAVE_OP_CONTENTION = BIT(DSI_EINT_INTERLEAVE_OP_CONTENTION),

	DSI_CMD_DMA_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_DMA_FIFO_UNDERFLOW),

	DSI_CMD_MDP_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_MDP_FIFO_UNDERFLOW),
@@ -292,7 +289,6 @@ enum dsi_error_int_type { 
	DSI_DLN1_LP1_CONTENTION = BIT(DSI_EINT_DLN1_LP1_CONTENTION),

	DSI_DLN2_LP1_CONTENTION = BIT(DSI_EINT_DLN2_LP1_CONTENTION),

	DSI_DLN3_LP1_CONTENTION = BIT(DSI_EINT_DLN3_LP1_CONTENTION),

	DSI_PANEL_SPECIFIC_ERR = BIT(DSI_EINT_PANEL_SPECIFIC_ERR),

};



/**

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+2 −2
Original line number Diff line number Diff line
@@ -801,7 +801,7 @@ static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len, 
	cmd->msg.tx_len = ((cmd_buf[5] << 8) | (cmd_buf[6]));



	if (cmd->msg.tx_len > payload_len) {

		pr_err("Incorrect payload length tx_len %ld, payload_len %d\n",

		pr_err("Incorrect payload length tx_len %zu, payload_len %d\n",

		       cmd->msg.tx_len, payload_len);

		return -EINVAL;

	}

drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c

+2 −2
Original line number Diff line number Diff line
@@ -659,7 +659,7 @@ int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy, 
	/* local vars */

	int rc = 0;

	u32 h_total, v_total;

	u64 inter_num;

	u32 inter_num;

	u32 num_of_lanes = 0;

	u32 bpp;

	u64 x, y;
@@ -688,7 +688,7 @@ int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy, 
	x = mult_frac(v_total * h_total, inter_num, num_of_lanes);

	y = rounddown(x, 1);



	clk_params.bitclk_mbps = rounddown(mult_frac(y, 1, 1000000), 1);

	clk_params.bitclk_mbps = rounddown(DIV_ROUND_UP_ULL(y, 1000000), 1);

	clk_params.escclk_numer = esc_clk_mhz;

	clk_params.escclk_denom = esc_clk_mmss_cc_prediv;

	clk_params.tlpx_numer_ns = tlpx_numer;

drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h

+3 −0
Original line number Diff line number Diff line
@@ -107,6 +107,9 @@ struct phy_timing_ops { 
		struct phy_timing_desc *desc);

};



#define roundup64(x, y) \

	({ u64 _tmp = (x)+(y)-1; do_div(_tmp, y); _tmp * y; })



/* DSI PHY timing functions for 14nm */

void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params);