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Commit a8721e28 authored by Mohammed Javid's avatar Mohammed Javid
Browse files

msm: ipa4: Update the missing config on sdx24 



Couple of missing config changes on sdx24 with
respect to EE_n_GSI_CH_k_QOS register,

 - USE_DB_ENG
	starting from sdx24, since there is no
	smart prefetch in MCS, this field should
	be 0 (for direct mode) for all channels,
	except for MHI with burst mode enabled.

 - MAX_PREFETCH
	This should be 0 (i.e, one prefetch buffer)

 - WRR_WEIGHT
	Software configurable, already taken care.

 - ESCAPE_BUFFER_ONLY
	update as per ep config excel.

Change-Id: Ib464f5b475f843ed0f913f737a1fe6f046969fc1
Signed-off-by: default avatarMohammed Javid <mjavid@codeaurora.org>
parent b7459312

drivers/platform/msm/ipa/ipa_clients/ipa_usb.c

+4 −1
Original line number Diff line number Diff line
@@ -1330,6 +1330,9 @@ static int ipa3_usb_request_xdci_channel( 
	chan_params.chan_params.ring_base_addr =

		params->xfer_ring_base_addr_iova;

	chan_params.chan_params.ring_base_vaddr = NULL;

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)

		chan_params.chan_params.use_db_eng = GSI_CHAN_DIRECT_MODE;

	else

		chan_params.chan_params.use_db_eng = GSI_CHAN_DB_MODE;

	chan_params.chan_params.max_prefetch = GSI_ONE_PREFETCH_SEG;

	if (params->dir == GSI_CHAN_DIR_FROM_GSI)

drivers/platform/msm/ipa/ipa_v3/ipa_dp.c

+10 −2
Original line number Diff line number Diff line
@@ -3813,6 +3813,9 @@ static int ipa_gsi_setup_channel(struct ipa_sys_connect_params *in, 
	ep->gsi_mem_info.chan_ring_base_vaddr =

		gsi_channel_props.ring_base_vaddr;



	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)

		gsi_channel_props.use_db_eng = GSI_CHAN_DIRECT_MODE;

	else

		gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE;

	gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG;

	if (ep->client == IPA_CLIENT_APPS_CMD_PROD)
@@ -4112,7 +4115,12 @@ int ipa_gsi_ch20_wa(void) 
		dma_alloc_coherent(ipa3_ctx->pdev, gsi_channel_props.ring_len,

		&dma_addr, 0);

	gsi_channel_props.ring_base_addr = dma_addr;



	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)

		gsi_channel_props.use_db_eng = GSI_CHAN_DIRECT_MODE;

	else

		gsi_channel_props.use_db_eng = GSI_CHAN_DB_MODE;



	gsi_channel_props.max_prefetch = GSI_ONE_PREFETCH_SEG;

	gsi_channel_props.low_weight = 1;

	gsi_channel_props.err_cb = ipa_gsi_chan_err_cb;

drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c

+16 −4
Original line number Diff line number Diff line
@@ -199,6 +199,7 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, 
	struct ipa3_ep_context *ep;

	const struct ipa_gsi_ep_config *ep_cfg;

	struct ipa_ep_cfg_ctrl ep_cfg_ctrl;

	bool burst_mode_enabled = false;



	IPA_MHI_FUNC_ENTRY();
@@ -281,7 +282,18 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, 
	ch_props.ring_len = params->ch_ctx_host->rlen;

	ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND(

			params->ch_ctx_host->rbase);



	if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT ||

		params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) {

		burst_mode_enabled = true;

	}



	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0 &&

		!burst_mode_enabled)

		ch_props.use_db_eng = GSI_CHAN_DIRECT_MODE;

	else

		ch_props.use_db_eng = GSI_CHAN_DB_MODE;



	ch_props.max_prefetch = GSI_ONE_PREFETCH_SEG;

	ch_props.low_weight = 1;

	ch_props.prefetch_mode = ep_cfg->prefetch_mode;
@@ -315,9 +327,9 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, 
			min(ep_cfg->ipa_if_tlv / 2, 8) * ch_props.re_size;

	}

	ch_scratch.mhi.oob_mod_threshold = 4;

	if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT ||

		params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) {

		ch_scratch.mhi.burst_mode_enabled = true;



	if (burst_mode_enabled) {

		ch_scratch.mhi.burst_mode_enabled = burst_mode_enabled;

		ch_scratch.mhi.polling_configuration =

			ipa3_mhi_get_ch_poll_cfg(client, params->ch_ctx_host,

				(ch_props.ring_len / ch_props.re_size));

drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c

+1 −0
Original line number Diff line number Diff line
@@ -935,6 +935,7 @@ static int ipa3_wdi2_gsi_alloc_channel_ring( 


	channel_props->use_db_eng = GSI_CHAN_DB_MODE;

	channel_props->max_prefetch = GSI_ONE_PREFETCH_SEG;

	channel_props->prefetch_mode = ep_cfg->prefetch_mode;

	channel_props->low_weight = 1;

	channel_props->err_cb = ipa_gsi_chan_err_cb;

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+28 −28
Original line number Diff line number Diff line
@@ -1872,80 +1872,80 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 3, 7, 6, 7, IPA_EE_AP } },

			{ 3, 7, 6, 7, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_USB_PROD]            = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 0, 5, 8, 9, IPA_EE_AP } },

			{ 0, 5, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_APPS_LAN_PROD]   = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 2, 6, 8, 9, IPA_EE_AP } },

			{ 2, 6, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_APPS_WAN_PROD] = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 12, IPA_EE_AP } },

			{ 1, 0, 8, 12, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_APPS_CMD_PROD]	  = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 6, 1, 20, 20, IPA_EE_AP } },

			{ 6, 1, 20, 20, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_Q6_WAN_PROD]         = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 4, 0, 8, 12, IPA_EE_Q6 } },

			{ 4, 0, 8, 12, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_Q6_CMD_PROD]	  = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 5, 1, 20, 20, IPA_EE_Q6 } },

			{ 5, 1, 20, 20, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_ETHERNET_PROD] = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 7, 0, 8, 10, IPA_EE_UC } },

			{ 7, 0, 8, 10, IPA_EE_UC, GSI_USE_PREFETCH_BUFS} },

	/* Only for test purpose */

	[IPA_4_2][IPA_CLIENT_TEST_PROD]           = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{0, 5, 8, 9, IPA_EE_AP } },

			{0, 5, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_TEST1_PROD]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 0, 5, 8, 9, IPA_EE_AP } },

			{ 0, 5, 8, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_TEST2_PROD]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 3, 7, 6, 7, IPA_EE_AP } },

			{ 3, 7, 6, 7, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_TEST3_PROD]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{1, 0, 8, 12, IPA_EE_AP } },

			{1, 0, 8, 12, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_TEST4_PROD]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 7, 10, 8, 10, IPA_EE_AP } },

			{ 7, 0, 8, 10, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },





	[IPA_4_2][IPA_CLIENT_WLAN1_CONS]          = {
@@ -1953,55 +1953,55 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 8, 6, 9, IPA_EE_AP } },

			{ 14, 8, 6, 9, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_USB_CONS]            = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 15, 9, 6, 6, IPA_EE_AP } },

			{ 15, 9, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_USB_DPL_CONS]        = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 12, 4, 4, 4, IPA_EE_AP } },

			{ 12, 4, 4, 4, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_APPS_LAN_CONS]       = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 8, 2, 6, 6, IPA_EE_AP } },

			{ 8, 2, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_APPS_WAN_CONS]       = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 9, 3, 6, 6, IPA_EE_AP } },

			{ 9, 3, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_Q6_LAN_CONS]         = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 11, 3, 6, 6, IPA_EE_Q6 } },

			{ 11, 3, 6, 6, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_Q6_WAN_CONS]         = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 10, 2, 6, 6, IPA_EE_Q6 } },

			{ 10, 2, 6, 6, IPA_EE_Q6,  GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 13, 4, 6, 6, IPA_EE_Q6 } },

			{ 13, 4, 6, 6, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_ETHERNET_CONS] = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 16, 1, 6, 6, IPA_EE_UC } },

			{ 16, 1, 6, 6, IPA_EE_UC, GSI_USE_PREFETCH_BUFS} },

	/* Only for test purpose */

	/* MBIM aggregation test pipes should have the same QMB as USB_CONS */

	[IPA_4_2][IPA_CLIENT_TEST_CONS]           = {
@@ -2009,38 +2009,38 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 15, 9, 6, 6, IPA_EE_AP } },

			{ 15, 9, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_TEST1_CONS]           = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 15, 9, 6, 6, IPA_EE_AP } },

			{ 15, 9, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_TEST2_CONS]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 12, 4, 4, 4, IPA_EE_AP } },

			{ 12, 4, 4, 4, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	[IPA_4_2][IPA_CLIENT_TEST3_CONS]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 8, 6, 9, IPA_EE_AP } },

			{ 14, 8, 6, 9, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },

	[IPA_4_2][IPA_CLIENT_TEST4_CONS]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 9, 3, 6, 6, IPA_EE_AP } },

			{ 9, 3, 6, 6, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY} },

	/* Dummy consumer (pipe 31) is used in L2TP rt rule */

	[IPA_4_2][IPA_CLIENT_DUMMY_CONS]          = {

			true, IPA_v4_2_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 31, 31, 8, 8, IPA_EE_AP } },

			{ 31, 31, 8, 8, IPA_EE_AP, GSI_USE_PREFETCH_BUFS} },



	/* IPA_4_5 */

	[IPA_4_5][IPA_CLIENT_WLAN1_PROD]          = {