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Commit a854aea2 authored by Mike Turquette's avatar Mike Turquette
Browse files

Merge tag 'socfpga-clk-update-for-v3.16' of... 

Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga

Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.
parents b4b3bfd0 0691bb1b

drivers/clk/socfpga/clk-gate.c

+0 −1
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ 
#define SOCFPGA_MMC_CLK			"sdmmc_clk"

#define SOCFPGA_GPIO_DB_CLK_OFFSET	0xA8



#define div_mask(width)	((1 << (width)) - 1)

#define streq(a, b) (strcmp((a), (b)) == 0)



#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)

drivers/clk/socfpga/clk-periph.c

+19 −3
Original line number Diff line number Diff line
@@ -29,12 +29,18 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, 
					     unsigned long parent_rate)

{

	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);

	u32 div;

	u32 div, val;



	if (socfpgaclk->fixed_div)

	if (socfpgaclk->fixed_div) {

		div = socfpgaclk->fixed_div;

	else

	} else {

		if (socfpgaclk->div_reg) {

			val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;

			val &= div_mask(socfpgaclk->width);

			parent_rate /= (val + 1);

		}

		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);

	}



	return parent_rate / div;

}
@@ -54,6 +60,7 @@ static __init void __socfpga_periph_init(struct device_node *node, 
	struct clk_init_data init;

	int rc;

	u32 fixed_div;

	u32 div_reg[3];



	of_property_read_u32(node, "reg", &reg);
@@ -63,6 +70,15 @@ static __init void __socfpga_periph_init(struct device_node *node, 


	periph_clk->hw.reg = clk_mgr_base_addr + reg;



	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);

	if (!rc) {

		periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];

		periph_clk->shift = div_reg[1];

		periph_clk->width = div_reg[2];

	} else {

		periph_clk->div_reg = 0;

	}



	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);

	if (rc)

		periph_clk->fixed_div = 0;

drivers/clk/socfpga/clk.h

+4 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#define CLKMGR_PERPLL_SRC	0xAC



#define SOCFPGA_MAX_PARENTS		3

#define div_mask(width) ((1 << (width)) - 1)



extern void __iomem *clk_mgr_base_addr;
@@ -52,6 +53,9 @@ struct socfpga_periph_clk { 
	struct clk_gate hw;

	char *parent_name;

	u32 fixed_div;

	void __iomem *div_reg;

	u32 width;      /* only valid if div_reg != 0 */

	u32 shift;      /* only valid if div_reg != 0 */

};



#endif /* SOCFPGA_CLK_H */