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Commit a804faa3 authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi
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ARM: dts: msm: Update proper clock domain address for LMH DCVS for SM6150 



Update correct OSM clock domain register address for LMH DCVS hardware
to get aggregated throttling request for each cluster for SM6150.

Change-Id: I383d235b1ebc4336303490fc3927374f00b50aa2
Signed-off-by: default avatarManaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
parent ea5e0ef1

arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18321000 0x1000>;

			<0x18323000 0x1000>;

		#thermal-sensor-cells = <0>;

	};
@@ -30,7 +30,7 @@ 
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18323000 0x1000>;

			<0x18325800 0x1000>;

		#thermal-sensor-cells = <0>;

	};

};