Merge "clk: qcom: Add support for GPU clocks for QCS405" (a76e79a1) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/clk-smd-rpm.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -605,6 +605,8 @@ DEFINE_CLK_SMD_RPM_QDSS(qcs405, qdss_clk, qdss_a_clk,
		QCOM_SMD_RPM_MISC_CLK, 1);
		DEFINE_CLK_SMD_RPM(qcs405, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
		DEFINE_CLK_SMD_RPM(qcs405, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
		DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk,
		QCOM_SMD_RPM_MEM_CLK, 0);

		/* SMD_XO_BUFFER */
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, bb_clk1, bb_clk1_a, 1);
		@@ -676,6 +678,8 @@ static struct clk_hw *qcs405_clks[] = {
		[RPM_SMD_CE1_A_CLK] = &qcs405_ce1_a_clk.hw,
		[RPM_SMD_QPIC_CLK] = &qcs405_qpic_clk.hw,
		[RPM_SMD_QPIC_A_CLK] = &qcs405_qpic_a_clk.hw,
		[RPM_SMD_BIMC_GPU_CLK] = &qcs405_bimc_gpu_clk.hw
		[RPM_SMD_BIMC_GPU_A_CLK] = &qcs405_bimc_gpu_a_clk.hw
		[PNOC_MSMBUS_CLK] = &pnoc_msmbus_clk.hw,
		[PNOC_MSMBUS_A_CLK] = &pnoc_msmbus_a_clk.hw,
		[PNOC_KEEPALIVE_A_CLK] = &pnoc_keepalive_a_clk.hw,
		@@ -706,7 +710,7 @@ static struct clk_hw *qcs405_clks[] = {

		static const struct rpm_smd_clk_desc rpm_clk_qcs405 = {
		.clks = qcs405_clks,
		.num_rpm_clks = RPM_SMD_CE1_A_CLK,
		.num_rpm_clks = RPM_SMD_BIMC_GPU_A_CLK,
		.num_clks = ARRAY_SIZE(qcs405_clks),
		};

drivers/clk/qcom/gcc-qcs405.c

+71 −0

Original line number	Diff line number	Diff line
		@@ -1404,6 +1404,19 @@ static struct clk_branch gcc_bimc_gfx_clk = {
		},
		};

		static struct clk_branch gcc_bimc_gpu_clk = {
		.halt_reg = 0x59030,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x59030,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_bimc_gpu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_bimc_mdss_clk = {
		.halt_reg = 0x31038,
		.halt_check = BRANCH_HALT,
		@@ -1837,6 +1850,32 @@ static struct clk_branch gcc_geni_ir_s_clk = {
		},
		};

		static struct clk_branch gcc_gfx_tcu_clk = {
		.halt_reg = 0x12020,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x4500C,
		.enable_mask = BIT(2),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_gfx_tcu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_gfx_tbu_clk = {
		.halt_reg = 0x12010,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x4500C,
		.enable_mask = BIT(3),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_gfx_tbu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_gp1_clk = {
		.halt_reg = 0x8000,
		.halt_check = BRANCH_HALT,
		@@ -1891,6 +1930,19 @@ static struct clk_branch gcc_gp3_clk = {
		},
		};

		static struct clk_branch gcc_gtcu_ahb_clk = {
		.halt_reg = 0x12044,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x4500C,
		.enable_mask = BIT(13),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_gtcu_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mdss_ahb_clk = {
		.halt_reg = 0x4d07c,
		.halt_check = BRANCH_HALT,
		@@ -2351,6 +2403,19 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
		},
		};

		static struct clk_branch gcc_smmu_cfg_clk = {
		.halt_reg = 0x12038,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x3600C,
		.enable_mask = BIT(12),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_smmu_cfg_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_sys_noc_usb3_clk = {
		.halt_reg = 0x26014,
		.halt_check = BRANCH_HALT,
		@@ -2650,6 +2715,11 @@ static struct clk_regmap *gcc_qcs405_clocks[] = {
		[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
		[GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
		&gcc_usb_hs_inactivity_timers_clk.clkr,
		[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
		[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
		[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
		[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
		[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
		};

		static const struct qcom_reset_map gcc_qcs405_resets[] = {
		@@ -2732,6 +2802,7 @@ static int gcc_qcs405_probe(struct platform_device *pdev)

		clk_set_rate(apss_ahb_clk_src.clkr.hw.clk, 19200000);
		clk_prepare_enable(apss_ahb_clk_src.clkr.hw.clk);
		clk_prepare_enable(gpll0_ao_out_main.clkr.hw.clk);

		dev_info(&pdev->dev, "Registered GCC clocks\n");

include/dt-bindings/clock/qcom,gcc-qcs405.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -143,6 +143,11 @@
		#define GPLL6_OUT_AUX 126
		#define MDSS_MDP_VOTE_CLK 127
		#define MDSS_ROTATOR_VOTE_CLK 128
		#define GCC_BIMC_GPU_CLK 129
		#define GCC_GTCU_AHB_CLK 130
		#define GCC_GFX_TCU_CLK 131
		#define GCC_GFX_TBU_CLK 132
		#define GCC_SMMU_CFG_CLK 133

		#define GCC_GENI_IR_BCR 0
		#define GCC_USB_HS_BCR 1

include/dt-bindings/clock/qcom,rpmcc.h

+9 −7

Original line number	Diff line number	Diff line
		@@ -105,13 +105,15 @@
		#define RPM_SMD_QPIC_A_CLK 65
		#define RPM_SMD_CE1_CLK 66
		#define RPM_SMD_CE1_A_CLK 67
		#define PNOC_MSMBUS_CLK 68
		#define PNOC_MSMBUS_A_CLK 69
		#define PNOC_KEEPALIVE_A_CLK 70
		#define SNOC_MSMBUS_CLK 71
		#define SNOC_MSMBUS_A_CLK 72
		#define BIMC_MSMBUS_CLK 73
		#define BIMC_MSMBUS_A_CLK 74
		#define RPM_SMD_BIMC_GPU_CLK 68
		#define RPM_SMD_BIMC_GPU_A_CLK 69
		#define PNOC_MSMBUS_CLK 70
		#define PNOC_MSMBUS_A_CLK 71
		#define PNOC_KEEPALIVE_A_CLK 72
		#define SNOC_MSMBUS_CLK 73
		#define SNOC_MSMBUS_A_CLK 74
		#define BIMC_MSMBUS_CLK 75
		#define BIMC_MSMBUS_A_CLK 76
		#define PNOC_USB_CLK 77
		#define PNOC_USB_A_CLK 78
		#define SNOC_USB_CLK 79