Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a746095c authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Enable DDI IO power domains in the DP MST path 



Commit 62b69566 ("drm/i915: Only enable DDI IO power domains after
enabling DPLL") changed how the DDI IO power domains get enabled, but
neglected the need to enable those domains when enabling a DP connector
with MST enabled, leading to

    Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler

Fixes: 62b69566 ("drm/i915: Only enable DDI IO power domains after enabling DPLL")
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170301141318.3607-2-ander.conselvan.de.oliveira@intel.com
parent 02e012f1

drivers/gpu/drm/i915/intel_dp_mst.c

+3 −0
Original line number Diff line number Diff line
@@ -163,6 +163,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, 
		intel_ddi_clk_select(&intel_dig_port->base,

				     pipe_config->shared_dpll);



		intel_display_power_get(dev_priv,

					intel_dig_port->ddi_io_power_domain);



		intel_prepare_dp_ddi_buffers(&intel_dig_port->base);

		intel_dp_set_link_params(intel_dp,

					 pipe_config->port_clock,