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Commit a65df1a7 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: enable dynamic clk switch feature for sm6150"

parents 15642b9a b309ce07

arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi

+14 −3
Original line number Diff line number Diff line
@@ -124,7 +124,9 @@ 


		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

			"src_byte_clk0", "src_pixel_clk0",

			"shadow_byte_clk0", "shadow_pixel_clk0";



		qcom,dsi-panel = <&dsi_hx83112a_truly_video>;

	};
@@ -213,8 +215,14 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;



		clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,

			 <&mdss_dsi0_pll PIX0_MUX_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0";

			 <&mdss_dsi0_pll PIX0_MUX_CLK>,

			 <&mdss_dsi0_pll BYTE0_SRC_CLK>,

			 <&mdss_dsi0_pll PIX0_SRC_CLK>,

			 <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>,

			 <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			"src_byte_clk0", "src_pixel_clk0",

			"shadow_byte_clk0", "shadow_pixel_clk0";

		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
@@ -358,6 +366,9 @@ 
	qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;

	qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;

	qcom,mdss-dsi-panel-status-read-length = <4>;

	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list =

		<924736320 909324048 913177120 917030184 920883256 928589392>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings =

arch/arm64/boot/dts/qcom/sm6150-sde-pll.dtsi

+6 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -17,11 +17,14 @@ 
		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0xae94400 0x588>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "gdsc_base";

		      <0xaf03000 0x8>,

		      <0xae94200 0x100>;

		reg-names = "pll_base", "gdsc_base",

			"dynamic_pll_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		memory-region = <&dfps_data_memory>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

arch/arm64/boot/dts/qcom/sm6150-sde.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -423,8 +423,10 @@ 
		label = "dsi-phy-0";

		cell-index = <0>;

		reg = <0xae94400 0x588>,

		    <0xae01400 0x100>;

		reg-names = "dsi_phy", "phy_clamp_base";

		    <0xae01400 0x100>,

		    <0xae94200 0x100>;

		reg-names = "dsi_phy", "phy_clamp_base",

			"dyn_refresh_base";

		vdda-0p9-supply = <&pm6150_l4>;

		qcom,platform-strength-ctrl = [ff 06

						ff 06

arch/arm64/boot/dts/qcom/sm6150.dtsi

+7 −2
Original line number Diff line number Diff line 
 /* Copyright (c) 2018, The Linux Foundation.All rights reserved.

 /* Copyright (c) 2018-2019, The Linux Foundation.All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -640,10 +640,15 @@ 
		};



		cont_splash_memory: cont_splash_region@9c000000 {

			reg = <0x0 0x9c000000 0x0 0x02400000>;

			reg = <0x0 0x9c000000 0x0 0x02300000>;

			label = "cont_splash_region";

		};



		dfps_data_memory: dfps_data_region@9e300000 {

			reg = <0x0 0x9e300000 0x0 0x0100000>;

			label = "dfps_data_region";

		};



		dump_mem: mem_dump_region {

			compatible = "shared-dma-pool";

			reusable;