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Commit a656ffcb authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by John W. Linville
Browse files

bcm47xx: make it possible to build bcm47xx without ssb. 



Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 08ccf572

arch/mips/Kconfig

+1 −7
Original line number Diff line number Diff line
@@ -91,15 +91,8 @@ config BCM47XX 
	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SSB

	select SSB_DRIVER_MIPS

	select SSB_DRIVER_EXTIF

	select SSB_EMBEDDED

	select SSB_B43_PCI_BRIDGE if PCI

	select SSB_PCICORE_HOSTMODE if PCI

	select GENERIC_GPIO

	select SYS_HAS_EARLY_PRINTK

	select CFE
@@ -788,6 +781,7 @@ endchoice 


source "arch/mips/alchemy/Kconfig"

source "arch/mips/ath79/Kconfig"

source "arch/mips/bcm47xx/Kconfig"

source "arch/mips/bcm63xx/Kconfig"

source "arch/mips/jazz/Kconfig"

source "arch/mips/jz4740/Kconfig"

arch/mips/bcm47xx/Kconfig

0 → 100644
+18 −0
Original line number Diff line number Diff line 
if BCM47XX



config BCM47XX_SSB

	bool "SSB Support for Broadcom BCM47XX"

	select SYS_HAS_CPU_MIPS32_R1

	select SSB

	select SSB_DRIVER_MIPS

	select SSB_DRIVER_EXTIF

	select SSB_EMBEDDED

	select SSB_B43_PCI_BRIDGE if PCI

	select SSB_PCICORE_HOSTMODE if PCI

	default y

	help

	 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.



	 This will generate an image with support for SSB and MIPS32 R1 instruction set.



endif

arch/mips/bcm47xx/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -3,4 +3,5 @@ 
# under Linux.

#



obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
 
obj-y 				+= gpio.o irq.o nvram.o prom.o serial.o setup.o time.o

obj-$(CONFIG_BCM47XX_SSB)	+= wgt634u.o

arch/mips/bcm47xx/gpio.c

+6 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); 
int gpio_request(unsigned gpio, const char *tag)

{

	switch (bcm47xx_bus_type) {

#ifdef CONFIG_BCM47XX_SSB

	case BCM47XX_BUS_TYPE_SSB:

		if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&

		    ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
@@ -34,6 +35,7 @@ int gpio_request(unsigned gpio, const char *tag) 
			return -EBUSY;



		return 0;

#endif

	}

	return -EINVAL;

}
@@ -42,6 +44,7 @@ EXPORT_SYMBOL(gpio_request); 
void gpio_free(unsigned gpio)

{

	switch (bcm47xx_bus_type) {

#ifdef CONFIG_BCM47XX_SSB

	case BCM47XX_BUS_TYPE_SSB:

		if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&

		    ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
@@ -53,6 +56,7 @@ void gpio_free(unsigned gpio) 


		clear_bit(gpio, gpio_in_use);

		return;

#endif

	}

}

EXPORT_SYMBOL(gpio_free);
@@ -60,6 +64,7 @@ EXPORT_SYMBOL(gpio_free); 
int gpio_to_irq(unsigned gpio)

{

	switch (bcm47xx_bus_type) {

#ifdef CONFIG_BCM47XX_SSB

	case BCM47XX_BUS_TYPE_SSB:

		if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco))

			return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2;
@@ -67,6 +72,7 @@ int gpio_to_irq(unsigned gpio) 
			return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2;

		else

			return -EINVAL;

#endif

	}

	return -EINVAL;

}

arch/mips/bcm47xx/nvram.c

+4 −0
Original line number Diff line number Diff line
@@ -26,7 +26,9 @@ static char nvram_buf[NVRAM_SPACE]; 
/* Probe for NVRAM header */

static void early_nvram_init(void)

{

#ifdef CONFIG_BCM47XX_SSB

	struct ssb_mipscore *mcore_ssb;

#endif

	struct nvram_header *header;

	int i;

	u32 base = 0;
@@ -35,11 +37,13 @@ static void early_nvram_init(void) 
	u32 *src, *dst;



	switch (bcm47xx_bus_type) {

#ifdef CONFIG_BCM47XX_SSB

	case BCM47XX_BUS_TYPE_SSB:

		mcore_ssb = &bcm47xx_bus.ssb.mipscore;

		base = mcore_ssb->flash_window;

		lim = mcore_ssb->flash_window_size;

		break;

#endif

	}



	off = FLASH_MIN;