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Commit a5f6ea29 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Linus Torvalds
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sh: prefix sh-specific "CCR" and "CCR2" by "SH_" 



Commit bcf24e1d ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.

sh-allmodconfig now fails with:

    include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
    make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1

This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h.  There's a similar issue with "CCR2"
on sh2a.

As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.

Signed-off-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 15c34a76

arch/sh/include/cpu-sh2/cpu/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
#define SH_CACHE_ASSOC		8



#if defined(CONFIG_CPU_SUBTYPE_SH7619)

#define CCR		0xffffffec

#define SH_CCR		0xffffffec



#define CCR_CACHE_CE	0x01	/* Cache enable */

#define CCR_CACHE_WT	0x02    /* CCR[bit1=1,bit2=1] */

arch/sh/include/cpu-sh2a/cpu/cache.h

+2 −2
Original line number Diff line number Diff line
@@ -17,8 +17,8 @@ 
#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define CCR		0xfffc1000 /* CCR1 */

#define CCR2		0xfffc1004

#define SH_CCR		0xfffc1000 /* CCR1 */

#define SH_CCR2		0xfffc1004



/*

 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not

arch/sh/include/cpu-sh3/cpu/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define CCR		0xffffffec	/* Address of Cache Control Register */

#define SH_CCR		0xffffffec	/* Address of Cache Control Register */



#define CCR_CACHE_CE	0x01	/* Cache Enable */

#define CCR_CACHE_WT	0x02	/* Write-Through (for P0,U0,P3) (else writeback) */

arch/sh/include/cpu-sh4/cpu/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define CCR		0xff00001c	/* Address of Cache Control Register */

#define SH_CCR		0xff00001c	/* Address of Cache Control Register */

#define CCR_CACHE_OCE	0x0001	/* Operand Cache Enable */

#define CCR_CACHE_WT	0x0002	/* Write-Through (for P0,U0,P3) (else writeback)*/

#define CCR_CACHE_CB	0x0004	/* Copy-Back (for P1) (else writethrough) */

arch/sh/kernel/cpu/init.c

+2 −2
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ static void cache_init(void) 
	unsigned long ccr, flags;



	jump_to_uncached();

	ccr = __raw_readl(CCR);

	ccr = __raw_readl(SH_CCR);



	/*

	 * At this point we don't know whether the cache is enabled or not - a
@@ -189,7 +189,7 @@ static void cache_init(void) 


	l2_cache_init();



	__raw_writel(flags, CCR);

	__raw_writel(flags, SH_CCR);

	back_to_cached();

}

#else