Commit a4ca2b2f authored Jun 18, 2015 by Bill Huang Committed by Thierry Reding Dec 17, 2015

clk: tegra: Fix WARN_ON in PLL_RE registration



This fixes two things.

- Read the correct IDDQ register
- Check the correct IDDQ bit position

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent afff455c

drivers/clk/tegra/clk-pll.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1735,7 +1735,8 @@ struct clk tegra_clk_register_pllre(const char name, const char *parent_name,

		val = pll_readl_base(pll);
		if (val & PLL_BASE_ENABLE)
		WARN_ON(val & pll_params->iddq_bit_idx);
		WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
		BIT(pll_params->iddq_bit_idx));
		else {
		int m;