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Commit a4c537c7 authored by G, Manjunath Kondaiah's avatar G, Manjunath Kondaiah Committed by Tony Lindgren
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OMAP: DMA: Replace read/write macros with functions 



Prepare DMA library to get converted into DMA driver using platform
device model and hwmod infrastucture(for omap2+, resource structures
for omap1)

The low level read/write macros are replaced with static inline
functions and register offsets are handled through static register
offset tables mapped through  enumeration constants.

These low level read/write functions along with static register offset
tables will be moved to respective mach-omap dma files in the later
patches of this series.

There are no functionality changes with these changes except change in
logic for handling 16bit registers of OMAP1.

Signed-off-by: default avatarG, Manjunath Kondaiah <manjugk@ti.com>
Tested-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Acked-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 447b8da5

arch/arm/plat-omap/dma.c

+316 −201

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/plat-omap/include/plat/dma.h

+29 −122
Original line number Diff line number Diff line
@@ -27,136 +27,14 @@ 
/* Hardware registers for omap1 */

#define OMAP1_DMA_BASE			(0xfffed800)



#define OMAP1_DMA_GCR			0x400

#define OMAP1_DMA_GSCR			0x404

#define OMAP1_DMA_GRST			0x408

#define OMAP1_DMA_HW_ID			0x442

#define OMAP1_DMA_PCH2_ID		0x444

#define OMAP1_DMA_PCH0_ID		0x446

#define OMAP1_DMA_PCH1_ID		0x448

#define OMAP1_DMA_PCHG_ID		0x44a

#define OMAP1_DMA_PCHD_ID		0x44c

#define OMAP1_DMA_CAPS_0_U		0x44e

#define OMAP1_DMA_CAPS_0_L		0x450

#define OMAP1_DMA_CAPS_1_U		0x452

#define OMAP1_DMA_CAPS_1_L		0x454

#define OMAP1_DMA_CAPS_2		0x456

#define OMAP1_DMA_CAPS_3		0x458

#define OMAP1_DMA_CAPS_4		0x45a

#define OMAP1_DMA_PCH2_SR		0x460

#define OMAP1_DMA_PCH0_SR		0x480

#define OMAP1_DMA_PCH1_SR		0x482

#define OMAP1_DMA_PCHD_SR		0x4c0



/* Hardware registers for omap2 and omap3 */

#define OMAP24XX_DMA4_BASE		(L4_24XX_BASE + 0x56000)

#define OMAP34XX_DMA4_BASE		(L4_34XX_BASE + 0x56000)

#define OMAP44XX_DMA4_BASE		(L4_44XX_BASE + 0x56000)



#define OMAP_DMA4_REVISION		0x00

#define OMAP_DMA4_GCR			0x78

#define OMAP_DMA4_IRQSTATUS_L0		0x08

#define OMAP_DMA4_IRQSTATUS_L1		0x0c

#define OMAP_DMA4_IRQSTATUS_L2		0x10

#define OMAP_DMA4_IRQSTATUS_L3		0x14

#define OMAP_DMA4_IRQENABLE_L0		0x18

#define OMAP_DMA4_IRQENABLE_L1		0x1c

#define OMAP_DMA4_IRQENABLE_L2		0x20

#define OMAP_DMA4_IRQENABLE_L3		0x24

#define OMAP_DMA4_SYSSTATUS		0x28

#define OMAP_DMA4_OCP_SYSCONFIG		0x2c

#define OMAP_DMA4_CAPS_0		0x64

#define OMAP_DMA4_CAPS_2		0x6c

#define OMAP_DMA4_CAPS_3		0x70

#define OMAP_DMA4_CAPS_4		0x74



#define OMAP1_LOGICAL_DMA_CH_COUNT	17

#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT	32	/* REVISIT: Is this 32 + 2? */



/* Common channel specific registers for omap1 */

#define OMAP1_DMA_CH_BASE(n)		(0x40 * (n) + 0x00)

#define OMAP1_DMA_CSDP(n)		(0x40 * (n) + 0x00)

#define OMAP1_DMA_CCR(n)		(0x40 * (n) + 0x02)

#define OMAP1_DMA_CICR(n)		(0x40 * (n) + 0x04)

#define OMAP1_DMA_CSR(n)		(0x40 * (n) + 0x06)

#define OMAP1_DMA_CEN(n)		(0x40 * (n) + 0x10)

#define OMAP1_DMA_CFN(n)		(0x40 * (n) + 0x12)

#define OMAP1_DMA_CSFI(n)		(0x40 * (n) + 0x14)

#define OMAP1_DMA_CSEI(n)		(0x40 * (n) + 0x16)

#define OMAP1_DMA_CPC(n)		(0x40 * (n) + 0x18)	/* 15xx only */

#define OMAP1_DMA_CSAC(n)		(0x40 * (n) + 0x18)

#define OMAP1_DMA_CDAC(n)		(0x40 * (n) + 0x1a)

#define OMAP1_DMA_CDEI(n)		(0x40 * (n) + 0x1c)

#define OMAP1_DMA_CDFI(n)		(0x40 * (n) + 0x1e)

#define OMAP1_DMA_CLNK_CTRL(n)		(0x40 * (n) + 0x28)



/* Common channel specific registers for omap2 */

#define OMAP_DMA4_CH_BASE(n)		(0x60 * (n) + 0x80)

#define OMAP_DMA4_CCR(n)		(0x60 * (n) + 0x80)

#define OMAP_DMA4_CLNK_CTRL(n)		(0x60 * (n) + 0x84)

#define OMAP_DMA4_CICR(n)		(0x60 * (n) + 0x88)

#define OMAP_DMA4_CSR(n)		(0x60 * (n) + 0x8c)

#define OMAP_DMA4_CSDP(n)		(0x60 * (n) + 0x90)

#define OMAP_DMA4_CEN(n)		(0x60 * (n) + 0x94)

#define OMAP_DMA4_CFN(n)		(0x60 * (n) + 0x98)

#define OMAP_DMA4_CSEI(n)		(0x60 * (n) + 0xa4)

#define OMAP_DMA4_CSFI(n)		(0x60 * (n) + 0xa8)

#define OMAP_DMA4_CDEI(n)		(0x60 * (n) + 0xac)

#define OMAP_DMA4_CDFI(n)		(0x60 * (n) + 0xb0)

#define OMAP_DMA4_CSAC(n)		(0x60 * (n) + 0xb4)

#define OMAP_DMA4_CDAC(n)		(0x60 * (n) + 0xb8)



/* Channel specific registers only on omap1 */

#define OMAP1_DMA_CSSA_L(n)		(0x40 * (n) + 0x08)

#define OMAP1_DMA_CSSA_U(n)		(0x40 * (n) + 0x0a)

#define OMAP1_DMA_CDSA_L(n)		(0x40 * (n) + 0x0c)

#define OMAP1_DMA_CDSA_U(n)		(0x40 * (n) + 0x0e)

#define OMAP1_DMA_COLOR_L(n)		(0x40 * (n) + 0x20)

#define OMAP1_DMA_COLOR_U(n)		(0x40 * (n) + 0x22)

#define OMAP1_DMA_CCR2(n)		(0x40 * (n) + 0x24)

#define OMAP1_DMA_LCH_CTRL(n)		(0x40 * (n) + 0x2a)	/* not on 15xx */

#define OMAP1_DMA_CCEN(n)		0

#define OMAP1_DMA_CCFN(n)		0



/* Channel specific registers only on omap2 */

#define OMAP_DMA4_CSSA(n)		(0x60 * (n) + 0x9c)

#define OMAP_DMA4_CDSA(n)		(0x60 * (n) + 0xa0)

#define OMAP_DMA4_CCEN(n)		(0x60 * (n) + 0xbc)

#define OMAP_DMA4_CCFN(n)		(0x60 * (n) + 0xc0)

#define OMAP_DMA4_COLOR(n)		(0x60 * (n) + 0xc4)



/* Additional registers available on OMAP4 */

#define OMAP_DMA4_CDP(n)		(0x60 * (n) + 0xd0)

#define OMAP_DMA4_CNDP(n)		(0x60 * (n) + 0xd4)

#define OMAP_DMA4_CCDN(n)		(0x60 * (n) + 0xd8)



/* Dummy defines to keep multi-omap compiles happy */

#define OMAP1_DMA_REVISION		0

#define OMAP1_DMA_IRQSTATUS_L0		0

#define OMAP1_DMA_IRQENABLE_L0		0

#define OMAP1_DMA_OCP_SYSCONFIG		0

#define OMAP_DMA4_HW_ID			0

#define OMAP_DMA4_CAPS_0_L		0

#define OMAP_DMA4_CAPS_0_U		0

#define OMAP_DMA4_CAPS_1_L		0

#define OMAP_DMA4_CAPS_1_U		0

#define OMAP_DMA4_GSCR			0

#define OMAP_DMA4_CPC(n)		0



#define OMAP_DMA4_LCH_CTRL(n)		0

#define OMAP_DMA4_COLOR_L(n)		0

#define OMAP_DMA4_COLOR_U(n)		0

#define OMAP_DMA4_CCR2(n)		0

#define OMAP1_DMA_CSSA(n)		0

#define OMAP1_DMA_CDSA(n)		0

#define OMAP_DMA4_CSSA_L(n)		0

#define OMAP_DMA4_CSSA_U(n)		0

#define OMAP_DMA4_CDSA_L(n)		0

#define OMAP_DMA4_CDSA_U(n)		0

#define OMAP1_DMA_COLOR(n)		0



/*----------------------------------------------------------------------------*/



/* DMA channels for omap1 */

#define OMAP_DMA_NO_DEVICE		0

#define OMAP_DMA_MCSI1_TX		1
@@ -405,6 +283,35 @@ 
#define DMA_CH_PRIO_HIGH		0x1

#define DMA_CH_PRIO_LOW			0x0 /* Def */



enum omap_reg_offsets {



GCR,		GSCR,		GRST1,		HW_ID,

PCH2_ID,	PCH0_ID,	PCH1_ID,	PCHG_ID,

PCHD_ID,	CAPS_0,		CAPS_1,		CAPS_2,

CAPS_3,		CAPS_4,		PCH2_SR,	PCH0_SR,

PCH1_SR,	PCHD_SR,	REVISION,	IRQSTATUS_L0,

IRQSTATUS_L1,	IRQSTATUS_L2,	IRQSTATUS_L3,	IRQENABLE_L0,

IRQENABLE_L1,	IRQENABLE_L2,	IRQENABLE_L3,	SYSSTATUS,

OCP_SYSCONFIG,



/* omap1+ specific */

CPC, CCR2, LCH_CTRL,



/* Common registers for all omap's */

CSDP,		CCR,		CICR,		CSR,

CEN,		CFN,		CSFI,		CSEI,

CSAC,		CDAC,		CDEI,

CDFI,		CLNK_CTRL,



/* Channel specific registers */

CSSA,		CDSA,		COLOR,

CCEN,		CCFN,



/* omap3630 and omap4 specific */

CDP,		CNDP,		CCDN,



};



enum omap_dma_burst_mode {

	OMAP_DMA_DATA_BURST_DIS = 0,

	OMAP_DMA_DATA_BURST_4,