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Commit a4847750 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Move to enabling GDSC control on SDM855 



The GDSCs are currently modelled as dummy regulators on SDM855.
Update their compatible properties to enable controlling them
from the GDSC regulator driver.

Change-Id: I887f491ecfb6233cc36006eaf36b6c519367dbbb
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent a831a16d

arch/arm64/boot/dts/qcom/sdm855-gdsc.dtsi

+29 −29
Original line number Diff line number Diff line
@@ -14,56 +14,56 @@ 
&soc {

	/* GDSCs in Global CC */

	emac_gdsc: qcom,gdsc@0x106004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "emac_gdsc";

		reg = <0x106004 0x4>;

		status = "disabled";

	};



	pcie_0_gdsc: qcom,gdsc@0x16b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "pcie_0_gdsc";

		reg = <0x16b004 0x4>;

		status = "disabled";

	};



	pcie_1_gdsc: qcom,gdsc@0x18d004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "pcie_1_gdsc";

		reg = <0x18d004 0x4>;

		status = "disabled";

	};



	ufs_card_gdsc: qcom,gdsc@0x175004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ufs_card_gdsc";

		reg = <0x175004 0x4>;

		status = "disabled";

	};



	ufs_phy_gdsc: qcom,gdsc@0x177004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ufs_phy_gdsc";

		reg = <0x177004 0x4>;

		status = "disabled";

	};



	usb30_prim_gdsc: qcom,gdsc@0x10f004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "usb30_prim_gdsc";

		reg = <0x10f004 0x4>;

		status = "disabled";

	};



	usb30_sec_gdsc: qcom,gdsc@0x110004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "usb30_sec_gdsc";

		reg = <0x110004 0x4>;

		status = "disabled";

	};



	hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@0x17d040 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";

		reg = <0x17d040 0x4>;

		qcom,no-status-check-on-disable;
@@ -72,7 +72,7 @@ 
	};



	hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@0x17d044 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";

		reg = <0x17d044 0x4>;

		qcom,no-status-check-on-disable;
@@ -81,7 +81,7 @@ 
	};



	hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@0x17d048 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";

		reg = <0x17d048 0x4>;

		qcom,no-status-check-on-disable;
@@ -90,7 +90,7 @@ 
	};



	hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@0x17d04c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";

		reg = <0x17d04c 0x4>;

		qcom,no-status-check-on-disable;
@@ -99,7 +99,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@0x17d050 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		reg = <0x17d050 0x4>;

		qcom,no-status-check-on-disable;
@@ -108,7 +108,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@0x17d054 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";

		reg = <0x17d054 0x4>;

		qcom,no-status-check-on-disable;
@@ -117,7 +117,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@0x17d058 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";

		reg = <0x17d058 0x4>;

		qcom,no-status-check-on-disable;
@@ -126,7 +126,7 @@ 
	};



	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@0x17d05c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";

		reg = <0x17d05c 0x4>;

		qcom,no-status-check-on-disable;
@@ -135,7 +135,7 @@ 
	};



	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@0x17d060 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";

		reg = <0x17d060 0x4>;

		qcom,no-status-check-on-disable;
@@ -145,42 +145,42 @@ 


	/* GDSCs in Camera CC */

	bps_gdsc: qcom,gdsc@0xad07004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "bps_gdsc";

		reg = <0xad07004 0x4>;

		status = "disabled";

	};



	ipe_0_gdsc: qcom,gdsc@0xad08004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ipe_0_gdsc";

		reg = <0xad08004 0x4>;

		status = "disabled";

	};



	ipe_1_gdsc: qcom,gdsc@0xad09004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ipe_1_gdsc";

		reg = <0xad09004 0x4>;

		status = "disabled";

	};



	ife_0_gdsc: qcom,gdsc@0xad0a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ife_0_gdsc";

		reg = <0xad0a004 0x4>;

		status = "disabled";

	};



	ife_1_gdsc: qcom,gdsc@0xad0b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ife_1_gdsc";

		reg = <0xad0b004 0x4>;

		status = "disabled";

	};



	titan_top_gdsc: qcom,gdsc@0xad0c1bc {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "titan_top_gdsc";

		reg = <0xad0c1bc 0x4>;

		status = "disabled";
@@ -188,7 +188,7 @@ 


	/* GDSCs in Display CC */

	mdss_core_gdsc: qcom,gdsc@0xaf03000 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mdss_core_gdsc";

		reg = <0xaf03000 0x4>;

		qcom,support-hw-trigger;
@@ -202,7 +202,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@0x2c9106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x2c9106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -222,7 +222,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@0x2c9100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x2c9100c 0x4>;

		domain-addr = <&gpu_gx_domain_addr>;
@@ -234,21 +234,21 @@ 


	/* GDSCs in Video CC */

	mvsc_gdsc: qcom,gdsc@0xab00814 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mvsc_gdsc";

		reg = <0xab00814 0x4>;

		status = "disabled";

	};



	mvs0_gdsc: qcom,gdsc@0xab00874 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mvs0_gdsc";

		reg = <0xab00874 0x4>;

		status = "disabled";

	};



	mvs1_gdsc: qcom,gdsc@0xab008b4 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mvs1_gdsc";

		reg = <0xab008b4 0x4>;

		status = "disabled";
@@ -256,7 +256,7 @@ 


	/* GDSCs in NPU CC */

	npu_core_gdsc: qcom,gdsc@0x9911028 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "npu_core_gdsc";

		reg = <0x9911028 0x4>;

		status = "disabled";