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Commit a43c9642 authored by Ondrej Jirman's avatar Ondrej Jirman Committed by Maxime Ripard
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clk: sunxi-ng: fix PLL_CPUX adjusting on H3 



When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).

Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.

Signed-off-by: default avatarOndrej Jirman <megous@megous.com>
Tested-by: default avatarLutz Sammer <johns98@gmx.net>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 7ce7d89f

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -803,6 +803,13 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = { 
	.num_resets	= ARRAY_SIZE(sun8i_h3_ccu_resets),

	.num_resets	= ARRAY_SIZE(sun8i_h3_ccu_resets),

};

};





static struct ccu_mux_nb sun8i_h3_cpu_nb = {

	.common		= &cpux_clk.common,

	.cm		= &cpux_clk.mux,

	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */

	.bypass_index	= 1, /* index of 24 MHz oscillator */

};



static void __init sun8i_h3_ccu_setup(struct device_node *node)

static void __init sun8i_h3_ccu_setup(struct device_node *node)

{

{

	void __iomem *reg;

	void __iomem *reg;
@@ -821,6 +828,9 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node) 
	writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);

	writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);





	sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);

	sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);



	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,

				  &sun8i_h3_cpu_nb);

}

}

CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",

CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",

	       sun8i_h3_ccu_setup);
 
	       sun8i_h3_ccu_setup);