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Commit a405bad5 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86: Add Haswell specific transaction flag reporting 



In the PEBS handler report the transaction flags using the new
generic transaction flags facility. Most of them come from
the "tsx_tuning" field in PEBSv2, but the abort code is derived
from the RAX register reported in the PEBS record.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1379688044-14173-3-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent fdfbbd07

arch/x86/kernel/cpu/perf_event_intel_ds.c

+20 −4
Original line number Diff line number Diff line
@@ -206,6 +206,8 @@ union hsw_tsx_tuning { 
	u64	    value;

};



#define PEBS_HSW_TSX_FLAGS	0xff00000000ULL



void init_debug_store_on_cpu(int cpu)

{

	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
@@ -807,6 +809,16 @@ static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs) 
	return 0;

}



static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)

{

	u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;



	/* For RTM XABORTs also log the abort code from AX */

	if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))

		txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;

	return txn;

}



static void __intel_pmu_pebs_event(struct perf_event *event,

				   struct pt_regs *iregs, void *__pebs)

{
@@ -885,11 +897,15 @@ static void __intel_pmu_pebs_event(struct perf_event *event, 
	    x86_pmu.intel_cap.pebs_format >= 1)

		data.addr = pebs->dla;



	/* Only set the TSX weight when no memory weight was requested. */

	if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll &&

	    (x86_pmu.intel_cap.pebs_format >= 2))

	if (x86_pmu.intel_cap.pebs_format >= 2) {

		/* Only set the TSX weight when no memory weight. */

		if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)

			data.weight = intel_hsw_weight(pebs);



		if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)

			data.txn = intel_hsw_transaction(pebs);

	}



	if (has_branch_stack(event))

		data.br_stack = &cpuc->lbr_stack;