Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a2952d89 authored by Zachary Amsden's avatar Zachary Amsden Committed by Andi Kleen
Browse files

[PATCH] paravirt: Preparatory mmu header movement 



Move header includes for the nopud / nopmd types to the location of the actual
pte / pgd type definitions.  This allows generic 4-level page type code to be
written before the split 2/3 level page table headers are included.

Signed-off-by: default avatarZachary Amsden <zach@vmware.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@muc.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
parent bd472c79

include/asm-i386/page.h

+2 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ typedef struct { unsigned long long pgprot; } pgprot_t; 
#define pte_val(x)	((x).pte_low | ((unsigned long long)(x).pte_high << 32))

#define __pmd(x) ((pmd_t) { (x) } )

#define HPAGE_SHIFT	21

#include <asm-generic/pgtable-nopud.h>

#else

typedef struct { unsigned long pte_low; } pte_t;

typedef struct { unsigned long pgd; } pgd_t;
@@ -59,6 +60,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; 
#define boot_pte_t pte_t /* or would you rather have a typedef */

#define pte_val(x)	((x).pte_low)

#define HPAGE_SHIFT	22

#include <asm-generic/pgtable-nopmd.h>

#endif

#define PTE_MASK	PAGE_MASK

include/asm-i386/pgtable-2level.h

+0 −2
Original line number Diff line number Diff line 
#ifndef _I386_PGTABLE_2LEVEL_H

#define _I386_PGTABLE_2LEVEL_H



#include <asm-generic/pgtable-nopmd.h>



#define pte_ERROR(e) \

	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)

#define pgd_ERROR(e) \

include/asm-i386/pgtable-3level.h

+0 −2
Original line number Diff line number Diff line 
#ifndef _I386_PGTABLE_3LEVEL_H

#define _I386_PGTABLE_3LEVEL_H



#include <asm-generic/pgtable-nopud.h>



/*

 * Intel Physical Address Extension (PAE) Mode - three-level page

 * tables on PPro+ CPUs.