Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a1369978 authored Sep 23, 2013 by Qipan Li Committed by Olof Johansson Sep 30, 2013

ARM: dts: sirf: fix fifosize, clks, dma channels for UART



sirf uart and usp-based uart driver with full dma support has
hit 3.12, here we fix the fifosize, dma channels for some HW
prop.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

parent 4dc3231f

arch/arm/boot/dts/atlas6.dtsi

+10 −0

Original line number	Diff line number	Diff line
		@@ -181,6 +181,8 @@
		interrupts = <17>;
		fifosize = <128>;
		clocks = <&clks 13>;
		sirf,uart-dma-rx-channel = <21>;
		sirf,uart-dma-tx-channel = <2>;
		};

		uart1: uart@b0060000 {
		@@ -199,6 +201,8 @@
		interrupts = <19>;
		fifosize = <128>;
		clocks = <&clks 15>;
		sirf,uart-dma-rx-channel = <6>;
		sirf,uart-dma-tx-channel = <7>;
		};

		usp0: usp@b0080000 {
		@@ -206,7 +210,10 @@
		compatible = "sirf,prima2-usp";
		reg = <0xb0080000 0x10000>;
		interrupts = <20>;
		fifosize = <128>;
		clocks = <&clks 28>;
		sirf,usp-dma-rx-channel = <17>;
		sirf,usp-dma-tx-channel = <18>;
		};

		usp1: usp@b0090000 {
		@@ -214,7 +221,10 @@
		compatible = "sirf,prima2-usp";
		reg = <0xb0090000 0x10000>;
		interrupts = <21>;
		fifosize = <128>;
		clocks = <&clks 29>;
		sirf,usp-dma-rx-channel = <14>;
		sirf,usp-dma-tx-channel = <15>;
		};

		dmac0: dma-controller@b00b0000 {

arch/arm/boot/dts/prima2.dtsi

+19 −3

Original line number	Diff line number	Diff line
		@@ -196,25 +196,32 @@
		uart0: uart@b0050000 {
		cell-index = <0>;
		compatible = "sirf,prima2-uart";
		reg = <0xb0050000 0x10000>;
		reg = <0xb0050000 0x1000>;
		interrupts = <17>;
		fifosize = <128>;
		clocks = <&clks 13>;
		sirf,uart-dma-rx-channel = <21>;
		sirf,uart-dma-tx-channel = <2>;
		};

		uart1: uart@b0060000 {
		cell-index = <1>;
		compatible = "sirf,prima2-uart";
		reg = <0xb0060000 0x10000>;
		reg = <0xb0060000 0x1000>;
		interrupts = <18>;
		fifosize = <32>;
		clocks = <&clks 14>;
		};

		uart2: uart@b0070000 {
		cell-index = <2>;
		compatible = "sirf,prima2-uart";
		reg = <0xb0070000 0x10000>;
		reg = <0xb0070000 0x1000>;
		interrupts = <19>;
		fifosize = <128>;
		clocks = <&clks 15>;
		sirf,uart-dma-rx-channel = <6>;
		sirf,uart-dma-tx-channel = <7>;
		};

		usp0: usp@b0080000 {
		@@ -222,7 +229,10 @@
		compatible = "sirf,prima2-usp";
		reg = <0xb0080000 0x10000>;
		interrupts = <20>;
		fifosize = <128>;
		clocks = <&clks 28>;
		sirf,usp-dma-rx-channel = <17>;
		sirf,usp-dma-tx-channel = <18>;
		};

		usp1: usp@b0090000 {
		@@ -230,7 +240,10 @@
		compatible = "sirf,prima2-usp";
		reg = <0xb0090000 0x10000>;
		interrupts = <21>;
		fifosize = <128>;
		clocks = <&clks 29>;
		sirf,usp-dma-rx-channel = <14>;
		sirf,usp-dma-tx-channel = <15>;
		};

		usp2: usp@b00a0000 {
		@@ -238,7 +251,10 @@
		compatible = "sirf,prima2-usp";
		reg = <0xb00a0000 0x10000>;
		interrupts = <22>;
		fifosize = <128>;
		clocks = <&clks 30>;
		sirf,usp-dma-rx-channel = <10>;
		sirf,usp-dma-tx-channel = <11>;
		};

		dmac0: dma-controller@b00b0000 {