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Commit a12cf0a8 authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68knommu: create bit definitions for the version 2 ColdFire cache controller 



The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 63e83c8a

arch/m68k/include/asm/m5206sim.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#define	CPU_NAME		"COLDFIRE(m5206)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m52xxacr.h>



/*

 *	Define the 5206 SIM register set addresses.

 */

arch/m68k/include/asm/m520xsim.h

+5 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#define	CPU_NAME		"COLDFIRE(m520x)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m52xxacr.h>



/*

 *  Define the 520x SIM register set addresses.

 */
@@ -57,6 +59,9 @@ 
#define MCFSIM_SDCS0        0x000a8110	/* SDRAM Chip Select 0 Configuration */

#define MCFSIM_SDCS1        0x000a8114	/* SDRAM Chip Select 1 Configuration */



/*

 * EPORT and GPIO registers.

 */

#define MCFEPORT_EPDDR			0xFC088002

#define MCFEPORT_EPDR			0xFC088004

#define MCFEPORT_EPPDR			0xFC088005

arch/m68k/include/asm/m523xsim.h

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#define	CPU_NAME		"COLDFIRE(m523x)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m52xxacr.h>



/*

 *	Define the 523x SIM register set addresses.

 */

arch/m68k/include/asm/m5249sim.h

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#define	CPU_NAME		"COLDFIRE(m5249)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m52xxacr.h>



/*

 *	Define the 5249 SIM register set addresses.

 */

arch/m68k/include/asm/m5272sim.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#define	CPU_NAME		"COLDFIRE(m5272)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m52xxacr.h>



/*

 *	Define the 5272 SIM register set addresses.

 */