Loading drivers/gpu/drm/msm/sde/sde_encoder.c +1 −1 Original line number Diff line number Diff line Loading @@ -1620,7 +1620,7 @@ static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc, struct msm_display_info *disp_info, bool is_dummy) { struct sde_encoder_phys *phys; int i, rc = 0; int i; u32 vsync_source; if (!sde_enc || !disp_info) { Loading drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c +1 −1 Original line number Diff line number Diff line Loading @@ -1119,7 +1119,7 @@ void reg_dmav1_setup_dspp_sixzonev17(struct sde_hw_dspp *ctx, void *cfg) struct sde_hw_cp_cfg *hw_cfg = cfg; struct sde_reg_dma_setup_ops_cfg dma_write_cfg; struct drm_msm_sixzone *sixzone; u32 reg = 0, hold = 0, local_hold = 0; u32 reg = 0, local_hold = 0; u32 opcode = 0, local_opcode = 0; int rc; Loading drivers/gpu/drm/msm/sde/sde_hw_top.c +2 −2 Original line number Diff line number Diff line Loading @@ -225,7 +225,7 @@ static void _update_vsync_source(struct sde_hw_mdp *mdp, struct sde_vsync_source_cfg *cfg) { struct sde_hw_blk_reg_map *c; u32 reg, wd_load_value, wd_ctl, wd_ctl2, i; u32 reg, wd_load_value, wd_ctl, wd_ctl2; if (!mdp || !cfg) return; Loading Loading @@ -285,7 +285,7 @@ static void sde_hw_setup_vsync_source(struct sde_hw_mdp *mdp, struct sde_vsync_source_cfg *cfg) { struct sde_hw_blk_reg_map *c; u32 reg, wd_load_value, wd_ctl, wd_ctl2, i; u32 reg, i; static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18}; if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber))) Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder.c +1 −1 Original line number Diff line number Diff line Loading @@ -1620,7 +1620,7 @@ static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc, struct msm_display_info *disp_info, bool is_dummy) { struct sde_encoder_phys *phys; int i, rc = 0; int i; u32 vsync_source; if (!sde_enc || !disp_info) { Loading
drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c +1 −1 Original line number Diff line number Diff line Loading @@ -1119,7 +1119,7 @@ void reg_dmav1_setup_dspp_sixzonev17(struct sde_hw_dspp *ctx, void *cfg) struct sde_hw_cp_cfg *hw_cfg = cfg; struct sde_reg_dma_setup_ops_cfg dma_write_cfg; struct drm_msm_sixzone *sixzone; u32 reg = 0, hold = 0, local_hold = 0; u32 reg = 0, local_hold = 0; u32 opcode = 0, local_opcode = 0; int rc; Loading
drivers/gpu/drm/msm/sde/sde_hw_top.c +2 −2 Original line number Diff line number Diff line Loading @@ -225,7 +225,7 @@ static void _update_vsync_source(struct sde_hw_mdp *mdp, struct sde_vsync_source_cfg *cfg) { struct sde_hw_blk_reg_map *c; u32 reg, wd_load_value, wd_ctl, wd_ctl2, i; u32 reg, wd_load_value, wd_ctl, wd_ctl2; if (!mdp || !cfg) return; Loading Loading @@ -285,7 +285,7 @@ static void sde_hw_setup_vsync_source(struct sde_hw_mdp *mdp, struct sde_vsync_source_cfg *cfg) { struct sde_hw_blk_reg_map *c; u32 reg, wd_load_value, wd_ctl, wd_ctl2, i; u32 reg, i; static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18}; if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber))) Loading