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Commit a0f82432 authored by Piotr Sroka's avatar Piotr Sroka Committed by Ulf Hansson
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mmc: sdhci-cadence: Fix writing PHY delay 



Add polling for ACK to be sure that data are written to PHY register.

Signed-off-by: default avatarPiotr Sroka <piotrs@cadence.com>
Reviewed-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent bf3240ba

drivers/mmc/host/sdhci-cadence.c

+9 −2
Original line number Diff line number Diff line
@@ -68,11 +68,12 @@ struct sdhci_cdns_priv { 
	bool enhanced_strobe;

};



static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,

static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,

				    u8 addr, u8 data)

{

	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;

	u32 tmp;

	int ret;



	tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |

	      (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
@@ -81,8 +82,14 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, 
	tmp |= SDHCI_CDNS_HRS04_WR;

	writel(tmp, reg);



	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);

	if (ret)

		return ret;



	tmp &= ~SDHCI_CDNS_HRS04_WR;

	writel(tmp, reg);



	return 0;

}



static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)