Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a0df399f authored by Lina Iyer's avatar Lina Iyer Committed by Andy Gross
Browse files

ARM64: dts: Add PSCI cpuidle support for MSM8916 



Add device bindings for CPUs to suspend using PSCI as the enable-method.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: default avatarLina Iyer <lina.iyer@linaro.org>
Tested-by: default avatarAndy Gross <andy.gross@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 3f452fe7

arch/arm64/boot/dts/qcom/msm8916.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -62,6 +62,8 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SPC>;

		};



		CPU1: cpu@1 {
@@ -69,6 +71,8 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x1>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SPC>;

		};



		CPU2: cpu@2 {
@@ -76,6 +80,8 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x2>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SPC>;

		};



		CPU3: cpu@3 {
@@ -83,12 +89,30 @@ 
			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x3>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SPC>;

		};



		L2_0: l2-cache {

		      compatible = "cache";

		      cache-level = <2>;

		};



		idle-states {

			CPU_SPC: spc {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x40000002>;

				entry-latency-us = <130>;

				exit-latency-us = <150>;

				min-residency-us = <2000>;

				local-timer-stop;

			};

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	timer {