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Commit a07d809a authored by Trishansh Bhardwaj's avatar Trishansh Bhardwaj
Browse files

msm: camera: icp: Reset if clock is enabled 



Reset IPE/BPS only if clock is enabled.

Change-Id: I6331b60b00af8eff02e1d072929df85e6502aa9d
Signed-off-by: default avatarTrishansh Bhardwaj <tbhardwa@codeaurora.org>
parent 10acbb72

drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c

+8 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -226,6 +226,13 @@ static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info, 
	bool reset_bps_top_fail = false;



	CAM_DBG(CAM_ICP, "CAM_ICP_BPS_CMD_RESET");



	if (!core_info->clk_enable || !core_info->cpas_start) {

		CAM_ERR(CAM_ICP, "BPS reset failed. clk_en %d cpas_start %d",

				core_info->clk_enable, core_info->cpas_start);

		return -EINVAL;

	}



	/* Reset BPS CDM core*/

	cam_io_w_mb((uint32_t)0xF,

		soc_info->reg_map[0].mem_base + BPS_CDM_RST_CMD);

drivers/media/platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c

+7 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -222,6 +222,12 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info, 
	bool reset_ipe_top_fail = false;



	CAM_DBG(CAM_ICP, "CAM_ICP_IPE_CMD_RESET");

	if (!core_info->clk_enable || !core_info->cpas_start) {

		CAM_ERR(CAM_HFI, "IPE reset failed. clk_en %d cpas_start %d",

				core_info->clk_enable, core_info->cpas_start);

		return -EINVAL;

	}



	/* IPE CDM core reset*/

	cam_io_w_mb((uint32_t)0xF,

		soc_info->reg_map[0].mem_base + IPE_CDM_RST_CMD);