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Commit a054c4d6 authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Thierry Reding
Browse files

pwm: sun4i: Drop legacy callbacks 



Remove the legacy callbacks .enable(), .disable(), .set_polarity() and
.config().

Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent c32c5c50

drivers/pwm/pwm-sun4i.c

+0 −160
Original line number Diff line number Diff line
@@ -305,167 +305,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 
	return 0;

}



static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,

			    int duty_ns, int period_ns)

{

	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);

	u32 prd, dty, val, clk_gate;

	u64 clk_rate, div = 0;

	unsigned int prescaler = 0;

	int err;



	clk_rate = clk_get_rate(sun4i_pwm->clk);



	if (sun4i_pwm->data->has_prescaler_bypass) {

		/* First, test without any prescaler when available */

		prescaler = PWM_PRESCAL_MASK;

		/*

		 * When not using any prescaler, the clock period in nanoseconds

		 * is not an integer so round it half up instead of

		 * truncating to get less surprising values.

		 */

		div = clk_rate * period_ns + NSEC_PER_SEC / 2;

		do_div(div, NSEC_PER_SEC);

		if (div - 1 > PWM_PRD_MASK)

			prescaler = 0;

	}



	if (prescaler == 0) {

		/* Go up from the first divider */

		for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {

			if (!prescaler_table[prescaler])

				continue;

			div = clk_rate;

			do_div(div, prescaler_table[prescaler]);

			div = div * period_ns;

			do_div(div, NSEC_PER_SEC);

			if (div - 1 <= PWM_PRD_MASK)

				break;

		}



		if (div - 1 > PWM_PRD_MASK) {

			dev_err(chip->dev, "period exceeds the maximum value\n");

			return -EINVAL;

		}

	}



	prd = div;

	div *= duty_ns;

	do_div(div, period_ns);

	dty = div;



	err = clk_prepare_enable(sun4i_pwm->clk);

	if (err) {

		dev_err(chip->dev, "failed to enable PWM clock\n");

		return err;

	}



	spin_lock(&sun4i_pwm->ctrl_lock);

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);



	if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {

		spin_unlock(&sun4i_pwm->ctrl_lock);

		clk_disable_unprepare(sun4i_pwm->clk);

		return -EBUSY;

	}



	clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

	if (clk_gate) {

		val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

		sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);

	}



	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);

	val |= BIT_CH(prescaler, pwm->hwpwm);

	sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);



	val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);

	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));



	if (clk_gate) {

		val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

		val |= clk_gate;

		sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);

	}



	spin_unlock(&sun4i_pwm->ctrl_lock);

	clk_disable_unprepare(sun4i_pwm->clk);



	return 0;

}



static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,

				  enum pwm_polarity polarity)

{

	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);

	u32 val;

	int ret;



	ret = clk_prepare_enable(sun4i_pwm->clk);

	if (ret) {

		dev_err(chip->dev, "failed to enable PWM clock\n");

		return ret;

	}



	spin_lock(&sun4i_pwm->ctrl_lock);

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);



	if (polarity != PWM_POLARITY_NORMAL)

		val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);

	else

		val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);



	sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);



	spin_unlock(&sun4i_pwm->ctrl_lock);

	clk_disable_unprepare(sun4i_pwm->clk);



	return 0;

}



static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)

{

	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);

	u32 val;

	int ret;



	ret = clk_prepare_enable(sun4i_pwm->clk);

	if (ret) {

		dev_err(chip->dev, "failed to enable PWM clock\n");

		return ret;

	}



	spin_lock(&sun4i_pwm->ctrl_lock);

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	val |= BIT_CH(PWM_EN, pwm->hwpwm);

	val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

	sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);

	spin_unlock(&sun4i_pwm->ctrl_lock);



	return 0;

}



static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)

{

	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);

	u32 val;



	spin_lock(&sun4i_pwm->ctrl_lock);

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	val &= ~BIT_CH(PWM_EN, pwm->hwpwm);

	val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

	sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);

	spin_unlock(&sun4i_pwm->ctrl_lock);



	clk_disable_unprepare(sun4i_pwm->clk);

}



static const struct pwm_ops sun4i_pwm_ops = {

	.config = sun4i_pwm_config,

	.set_polarity = sun4i_pwm_set_polarity,

	.enable = sun4i_pwm_enable,

	.disable = sun4i_pwm_disable,

	.apply = sun4i_pwm_apply,

	.get_state = sun4i_pwm_get_state,

	.owner = THIS_MODULE,