Commit 9fe2989c authored Oct 12, 2017 by Chen-Yu Tsai Committed by Greg Kroah-Hartman Dec 25, 2017

clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider




[ Upstream commit d51fe3ba9773c8b6fc79f82bbe75d64baf604292 ]

The post-divider for the audio PLL is in bits [29:26], as specified
in the user manual, not [19:16] as currently programmed in the code.
The post-divider has a default register value of 2, i.e. a divider
of 3. This means the clock rate fed to the audio codec would be off.

This was discovered when porting sigma-delta modulation for the PLL
to sun5i, which needs the post-divider to be 1.

Fix the bit offset, so we do actually force the post-divider to a
certain value.

Fixes: 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent a7455b11

drivers/clk/sunxi-ng/ccu-sun5i.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -982,8 +982,8 @@ static void __init sun5i_ccu_init(struct device_node *node,

		/* Force the PLL-Audio-1x divider to 4 */
		val = readl(reg + SUN5I_PLL_AUDIO_REG);
		val &= ~GENMASK(19, 16);
		writel(val \| (3 << 16), reg + SUN5I_PLL_AUDIO_REG);
		val &= ~GENMASK(29, 26);
		writel(val \| (3 << 26), reg + SUN5I_PLL_AUDIO_REG);

		/*
		* Use the peripheral PLL as the AHB parent, instead of CPU /